3 * Configuration settings for the Armadeus Project motherboard APF27
5 * Copyright (C) 2008-2013 Eric Jarrige <eric.jarrige@armadeus.org>
7 * SPDX-License-Identifier: GPL-2.0+
13 #define CONFIG_VERSION_VARIABLE
14 #define CONFIG_ENV_VERSION 10
15 #define CONFIG_IDENT_STRING " apf27 patch 3.10"
16 #define CONFIG_BOARD_NAME apf27
21 #define CONFIG_ARM926EJS /* this is an ARM926EJS CPU */
22 #define CONFIG_MX27 /* in a Freescale i.MX27 Chip */
23 #define CONFIG_MACH_TYPE 1698 /* APF27 */
24 #define CONFIG_SYS_GENERIC_BOARD
27 * Enable the call to miscellaneous platform dependent initialization.
29 #define CONFIG_SYS_NO_FLASH /* to be define before <config_cmd_default.h> */
32 * Board display option
34 #define CONFIG_DISPLAY_BOARDINFO
35 #define CONFIG_DISPLAY_CPUINFO
40 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
41 #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds"
42 #define CONFIG_SPL_MAX_SIZE 2048
43 #define CONFIG_SPL_TEXT_BASE 0xA0000000
45 /* NAND boot config */
46 #define CONFIG_SPL_NAND_SUPPORT
47 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
48 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x800
49 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
50 #define CONFIG_SYS_NAND_U_BOOT_SIZE CONFIG_SYS_MONITOR_LEN - 0x800
55 #define CONFIG_BOOTP_SUBNETMASK
56 #define CONFIG_BOOTP_GATEWAY
57 #define CONFIG_BOOTP_HOSTNAME
58 #define CONFIG_BOOTP_BOOTPATH
59 #define CONFIG_BOOTP_BOOTFILESIZE
60 #define CONFIG_BOOTP_DNS
61 #define CONFIG_BOOTP_DNS2
63 #define CONFIG_HOSTNAME CONFIG_BOARD_NAME
64 #define CONFIG_ROOTPATH "/tftpboot/" __stringify(CONFIG_BOARD_NAME) "-root"
69 #include <config_cmd_default.h>
71 #define CONFIG_CMD_ASKENV /* ask for env variable */
72 #define CONFIG_CMD_BSP /* Board Specific functions */
73 #define CONFIG_CMD_CACHE /* icache, dcache */
74 #define CONFIG_CMD_DATE
75 #define CONFIG_CMD_DHCP /* DHCP Support */
76 #define CONFIG_CMD_DNS
77 #define CONFIG_CMD_EEPROM
78 #define CONFIG_CMD_EXT2
79 #define CONFIG_CMD_FAT /* FAT support */
80 #define CONFIG_CMD_IMX_FUSE /* imx iim fuse */
81 #define CONFIG_CMD_I2C
82 #define CONFIG_CMD_MII /* MII support */
83 #define CONFIG_CMD_MMC
84 #define CONFIG_CMD_MTDPARTS /* MTD partition support */
85 #define CONFIG_CMD_NAND /* NAND support */
86 #define CONFIG_CMD_NAND_LOCK_UNLOCK
87 #define CONFIG_CMD_NAND_TRIMFFS
88 #define CONFIG_CMD_NFS /* NFS support */
89 #define CONFIG_CMD_PING /* ping support */
90 #define CONFIG_CMD_SETEXPR /* setexpr support */
91 #define CONFIG_CMD_UBI
92 #define CONFIG_CMD_UBIFS
95 * Memory configurations
97 #define CONFIG_NR_DRAM_POPULATED 1
98 #define CONFIG_NR_DRAM_BANKS 2
100 #define ACFG_SDRAM_MBYTE_SYZE 64
102 #define PHYS_SDRAM_1 0xA0000000
103 #define PHYS_SDRAM_2 0xB0000000
104 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
105 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (512<<10))
106 #define CONFIG_SYS_MEMTEST_START 0xA0000000 /* memtest test area */
107 #define CONFIG_SYS_MEMTEST_END 0xA0300000 /* 3 MiB RAM test */
109 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE \
110 + PHYS_SDRAM_1_SIZE - 0x0100000)
112 #define CONFIG_SYS_TEXT_BASE 0xA0000800
117 #define ACFG_MONITOR_OFFSET 0x00000000
118 #define CONFIG_SYS_MONITOR_LEN 0x00100000 /* 1MiB */
119 #define CONFIG_ENV_IS_IN_NAND
120 #define CONFIG_ENV_OVERWRITE
121 #define CONFIG_ENV_OFFSET 0x00100000 /* NAND offset */
122 #define CONFIG_ENV_SIZE 0x00020000 /* 128kB */
123 #define CONFIG_ENV_RANGE 0X00080000 /* 512kB */
124 #define CONFIG_ENV_OFFSET_REDUND \
125 (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE) /* +512kB */
126 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE /* 512kB */
127 #define CONFIG_FIRMWARE_OFFSET 0x00200000
128 #define CONFIG_FIRMWARE_SIZE 0x00080000 /* 512kB */
129 #define CONFIG_KERNEL_OFFSET 0x00300000
130 #define CONFIG_ROOTFS_OFFSET 0x00800000
132 #define CONFIG_MTDMAP "mxc_nand.0"
133 #define MTDIDS_DEFAULT "nand0=" CONFIG_MTDMAP
134 #define MTDPARTS_DEFAULT "mtdparts=" CONFIG_MTDMAP \
144 * U-Boot general configurations
146 #define CONFIG_SYS_LONGHELP
147 #define CONFIG_SYS_PROMPT "BIOS> " /* prompt string */
148 #define CONFIG_SYS_CBSIZE 2048 /* console I/O buffer */
149 #define CONFIG_SYS_PBSIZE \
150 (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
151 /* Print buffer size */
152 #define CONFIG_SYS_MAXARGS 16 /* max command args */
153 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
154 /* Boot argument buffer size */
155 #define CONFIG_AUTO_COMPLETE
156 #define CONFIG_CMDLINE_EDITING
157 #define CONFIG_SYS_HUSH_PARSER /* enable the "hush" shell */
158 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " /* secondary prompt string */
159 #define CONFIG_ENV_VARS_UBOOT_CONFIG
160 #define CONFIG_PREBOOT "run check_flash check_env;"
166 #define CONFIG_CMDLINE_TAG /* send commandline to Kernel */
167 #define CONFIG_SETUP_MEMORY_TAGS /* send memory definition to kernel */
168 #define CONFIG_INITRD_TAG /* send initrd params */
170 #define CONFIG_OF_LIBFDT
172 #define CONFIG_BOOTDELAY 5
173 #define CONFIG_ZERO_BOOTDELAY_CHECK
174 #define CONFIG_BOOTFILE __stringify(CONFIG_BOARD_NAME) "-linux.bin"
175 #define CONFIG_BOOTARGS "console=" __stringify(ACFG_CONSOLE_DEV) "," \
176 __stringify(CONFIG_BAUDRATE) " " MTDPARTS_DEFAULT \
177 " ubi.mtd=rootfs root=ubi0:rootfs rootfstype=ubifs "
179 #define ACFG_CONSOLE_DEV ttySMX0
180 #define CONFIG_BOOTCOMMAND "run ubifsboot"
181 #define CONFIG_SYS_AUTOLOAD "no"
183 * Default load address for user programs and kernel
185 #define CONFIG_LOADADDR 0xA0000000
186 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
191 #define CONFIG_EXTRA_ENV_SETTINGS \
192 "env_version=" __stringify(CONFIG_ENV_VERSION) "\0" \
193 "consoledev=" __stringify(ACFG_CONSOLE_DEV) "\0" \
194 "mtdparts=" MTDPARTS_DEFAULT "\0" \
195 "partition=nand0,6\0" \
196 "u-boot_addr=" __stringify(ACFG_MONITOR_OFFSET) "\0" \
197 "env_addr=" __stringify(CONFIG_ENV_OFFSET) "\0" \
198 "firmware_addr=" __stringify(CONFIG_FIRMWARE_OFFSET) "\0" \
199 "firmware_size=" __stringify(CONFIG_FIRMWARE_SIZE) "\0" \
200 "kernel_addr=" __stringify(CONFIG_KERNEL_OFFSET) "\0" \
201 "rootfs_addr=" __stringify(CONFIG_ROOTFS_OFFSET) "\0" \
202 "board_name=" __stringify(CONFIG_BOARD_NAME) "\0" \
203 "kernel_addr_r=A0000000\0" \
204 "check_env=if test -n ${flash_env_version}; " \
205 "then env default env_version; " \
206 "else env set flash_env_version ${env_version}; env save; "\
208 "if itest ${flash_env_version} < ${env_version}; then " \
209 "echo \"*** Warning - Environment version" \
210 " change suggests: run flash_reset_env; reset\"; "\
211 "env default flash_reset_env; "\
213 "check_flash=nand lock; nand unlock ${env_addr}; \0" \
214 "flash_reset_env=env default -f -a; saveenv; run update_env;" \
215 "echo Flash environment variables erased!\0" \
216 "download_uboot=tftpboot ${loadaddr} ${board_name}" \
217 "-u-boot-with-spl.bin\0" \
218 "flash_uboot=nand unlock ${u-boot_addr} ;" \
219 "nand erase.part u-boot;" \
220 "if nand write.trimffs ${fileaddr} ${u-boot_addr} ${filesize};"\
221 "then nand lock; nand unlock ${env_addr};" \
222 "echo Flashing of uboot succeed;" \
223 "else echo Flashing of uboot failed;" \
225 "update_uboot=run download_uboot flash_uboot\0" \
226 "download_env=tftpboot ${loadaddr} ${board_name}" \
227 "-u-boot-env.txt\0" \
228 "flash_env=env import -t ${loadaddr}; env save; \0" \
229 "update_env=run download_env flash_env\0" \
230 "update_all=run update_env update_uboot\0" \
231 "unlock_regs=mw 10000008 0; mw 10020008 0\0" \
236 #define CONFIG_MXC_UART
237 #define CONFIG_CONS_INDEX 1
238 #define CONFIG_BAUDRATE 115200
239 #define CONFIG_MXC_UART_BASE UART1_BASE
244 #define CONFIG_MXC_GPIO
253 #define CONFIG_NAND_MXC
255 #define CONFIG_MXC_NAND_REGS_BASE 0xD8000000
256 #define CONFIG_SYS_NAND_BASE CONFIG_MXC_NAND_REGS_BASE
257 #define CONFIG_SYS_MAX_NAND_DEVICE 1
259 #define CONFIG_MXC_NAND_HWECC
260 #define CONFIG_SYS_NAND_LARGEPAGE
261 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT
262 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
263 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
264 #define CONFIG_SYS_NAND_PAGE_COUNT CONFIG_SYS_NAND_BLOCK_SIZE / \
265 CONFIG_SYS_NAND_PAGE_SIZE
266 #define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024)
267 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 11
268 #define NAND_MAX_CHIPS 1
270 #define CONFIG_FLASH_SHOW_PROGRESS 45
271 #define CONFIG_SYS_NAND_QUIET 1
274 * Partitions & Filsystems
276 #define CONFIG_MTD_DEVICE
277 #define CONFIG_MTD_PARTITIONS
278 #define CONFIG_DOS_PARTITION
279 #define CONFIG_SUPPORT_VFAT
284 #define CONFIG_RBTREE
288 * Ethernet (on SOC imx FEC)
290 #define CONFIG_FEC_MXC
291 #define CONFIG_FEC_MXC_PHYADDR 0x1f
292 #define CONFIG_MII /* MII PHY management */
297 #ifndef CONFIG_SPL_BUILD
300 #define CONFIG_FPGA_COUNT 1
301 #define CONFIG_FPGA_XILINX
302 #define CONFIG_FPGA_SPARTAN3
303 #define CONFIG_SYS_FPGA_WAIT 250 /* 250 ms */
304 #define CONFIG_SYS_FPGA_PROG_FEEDBACK
305 #define CONFIG_SYS_FPGA_CHECK_CTRLC
306 #define CONFIG_SYS_FPGA_CHECK_ERROR
311 #ifdef CONFIG_CMD_IMX_FUSE
312 #define IIM_MAC_BANK 0
313 #define IIM_MAC_ROW 5
314 #define IIM0_SCC_KEY 11
322 #ifdef CONFIG_CMD_I2C
323 #define CONFIG_SYS_I2C
324 #define CONFIG_SYS_I2C_MXC
325 #define CONFIG_SYS_MXC_I2C1_SPEED 100000 /* 100 kHz */
326 #define CONFIG_SYS_MXC_I2C1_SLAVE 0x7F
327 #define CONFIG_SYS_MXC_I2C2_SPEED 100000 /* 100 kHz */
328 #define CONFIG_SYS_MXC_I2C2_SLAVE 0x7F
329 #define CONFIG_SYS_I2C_NOPROBES { }
331 #ifdef CONFIG_CMD_EEPROM
332 # define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM 24LC02 */
333 # define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
334 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
335 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* msec */
336 #endif /* CONFIG_CMD_EEPROM */
337 #endif /* CONFIG_CMD_I2C */
342 #ifdef CONFIG_CMD_MMC
344 #define CONFIG_GENERIC_MMC
345 #define CONFIG_MXC_MMC
346 #define CONFIG_MXC_MCI_REGS_BASE 0x10014000
352 #ifdef CONFIG_CMD_DATE
353 #define CONFIG_RTC_DS1374
354 #define CONFIG_SYS_RTC_BUS_NUM 0
355 #endif /* CONFIG_CMD_DATE */
360 * 31 | x |x| x x x x |x x x x x x x x x x |x x|x x x x|x x x x x x x x x x| 0
361 * |CPLM|X|----PD---|--------MFD---------|XXX|--MFI--|-----MFN-----------|
363 #define CONFIG_MX27_CLK32 32768 /* 32768 or 32000 Hz crystal */
365 #if (ACFG_SDRAM_MBYTE_SYZE == 64) /* micron MT46H16M32LF -6 */
367 #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
368 #define PHYS_SDRAM_2_SIZE 0x04000000 /* 64 MB */
371 #if (ACFG_SDRAM_MBYTE_SYZE == 128)
373 #define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
374 #define PHYS_SDRAM_2_SIZE 0x08000000 /* 128 MB */
377 #if (ACFG_SDRAM_MBYTE_SYZE == 256)
379 #define PHYS_SDRAM_1_SIZE 0x10000000 /* 256 MB */
380 #define PHYS_SDRAM_2_SIZE 0x10000000 /* 256 MB */
383 #endif /* __CONFIG_H */