git.sur5r.net Git - u-boot/blob - include/configs/aria.h

   1 /*
   2  * (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
   3  * (C) Copyright 2009, DAVE Srl <www.dave.eu>
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * Aria board configuration file
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 #define CONFIG_ARIA 1
  32 /*
  33  * Memory map for the ARIA board:
  34  *
  35  * 0x0000_0000-0x0FFF_FFFF      DDR RAM (256 MB)
  36  * 0x3000_0000-0x3001_FFFF      On Chip SRAM (128 KB)
  37  * 0x3010_0000-0x3011_FFFF      On Board SRAM (128 KB) - CS6
  38  * 0x3020_0000-0x3021_FFFF      FPGA (128 KB) - CS2
  39  * 0x8000_0000-0x803F_FFFF      IMMR (4 MB)
  40  * 0x8400_0000-0x82FF_FFFF      PCI I/O space (16 MB)
  41  * 0xA000_0000-0xAFFF_FFFF      PCI memory space (256 MB)
  42  * 0xB000_0000-0xBFFF_FFFF      PCI memory mapped I/O space (256 MB)
  43  * 0xFC00_0000-0xFFFF_FFFF      NOR Boot FLASH (64 MB)
  44  */
  45
  46 /*
  47  * High Level Configuration Options
  48  */
  49 #define CONFIG_E300             1       /* E300 Family */
  50 #define CONFIG_MPC512X          1       /* MPC512X family */
  51 #define CONFIG_FSL_DIU_FB       1       /* FSL DIU */
  52 #define CONFIG_FSL_DIU_LOGO_BMP 1       /* Don't include FSL DIU binary bmp */
  53
  54 /* video */
  55 #undef CONFIG_VIDEO
  56
  57 #if defined(CONFIG_VIDEO)
  58 #define CONFIG_CFB_CONSOLE
  59 #define CONFIG_VGA_AS_SINGLE_DEVICE
  60 #endif
  61
  62 /* CONFIG_PCI is defined at config time */
  63
  64 #define CONFIG_SYS_MPC512X_CLKIN        33000000        /* in Hz */
  65
  66 #define CONFIG_BOARD_EARLY_INIT_F               /* call board_early_init_f() */
  67 #define CONFIG_MISC_INIT_R
  68
  69 #define CONFIG_SYS_IMMR                 0x80000000
  70 #define CONFIG_SYS_DIU_ADDR             (CONFIG_SYS_IMMR+0x2100)
  71
  72 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest region */
  73 #define CONFIG_SYS_MEMTEST_END          0x00400000
  74
  75 /*
  76  * DDR Setup - manually set all parameters as there's no SPD etc.
  77  */
  78 #define CONFIG_SYS_DDR_SIZE             256             /* MB */
  79 #define CONFIG_SYS_DDR_BASE             0x00000000
  80 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  81
  82 /* DDR Controller Configuration
  83  *
  84  * SYS_CFG:
  85  *      [31:31] MDDRC Soft Reset:       Diabled
  86  *      [30:30] DRAM CKE pin:           Enabled
  87  *      [29:29] DRAM CLK:               Enabled
  88  *      [28:28] Command Mode:           Enabled (For initialization only)
  89  *      [27:25] DRAM Row Select:        dram_row[15:0] = magenta_address[25:10]
  90  *      [24:21] DRAM Bank Select:       dram_bank[1:0] = magenta_address[11:10]
  91  *      [20:19] Read Test:              DON'T USE
  92  *      [18:18] Self Refresh:           Enabled
  93  *      [17:17] 16bit Mode:             Disabled
  94  *      [16:13] Ready Delay:            2
  95  *      [12:12] Half DQS Delay:         Disabled
  96  *      [11:11] Quarter DQS Delay:      Disabled
  97  *      [10:08] Write Delay:            2
  98  *      [07:07] Early ODT:              Disabled
  99  *      [06:06] On DIE Termination:     Disabled
 100  *      [05:05] FIFO Overflow Clear:    DON'T USE here
 101  *      [04:04] FIFO Underflow Clear:   DON'T USE here
 102  *      [03:03] FIFO Overflow Pending:  DON'T USE here
 103  *      [02:02] FIFO Underlfow Pending: DON'T USE here
 104  *      [01:01] FIFO Overlfow Enabled:  Enabled
 105  *      [00:00] FIFO Underflow Enabled: Enabled
 106  * TIME_CFG0
 107  *      [31:16] DRAM Refresh Time:      0 CSB clocks
 108  *      [15:8]  DRAM Command Time:      0 CSB clocks
 109  *      [07:00] DRAM Precharge Time:    0 CSB clocks
 110  * TIME_CFG1
 111  *      [31:26] DRAM tRFC:
 112  *      [25:21] DRAM tWR1:
 113  *      [20:17] DRAM tWRT1:
 114  *      [16:11] DRAM tDRR:
 115  *      [10:05] DRAM tRC:
 116  *      [04:00] DRAM tRAS:
 117  * TIME_CFG2
 118  *      [31:28] DRAM tRCD:
 119  *      [27:23] DRAM tFAW:
 120  *      [22:19] DRAM tRTW1:
 121  *      [18:15] DRAM tCCD:
 122  *      [14:10] DRAM tRTP:
 123  *      [09:05] DRAM tRP:
 124  *      [04:00] DRAM tRPA
 125  */
 126 #define CONFIG_SYS_MDDRC_SYS_CFG        0xF8604A00
 127 #define CONFIG_SYS_MDDRC_SYS_CFG_RUN    0xE8604A00
 128 /*#define CONFIG_SYS_MDDRC_TIME_CFG1    0x54EC1168 */
 129   #define CONFIG_SYS_MDDRC_TIME_CFG1    0x55D81189
 130 /*#define CONFIG_SYS_MDDRC_TIME_CFG2    0x35210864 */
 131   #define CONFIG_SYS_MDDRC_TIME_CFG2    0x34790863
 132
 133 #define CONFIG_SYS_MDDRC_SYS_CFG_EN     0xF0000000
 134 #define CONFIG_SYS_MDDRC_TIME_CFG0      0x00003D2E
 135 /*#define CONFIG_SYS_MDDRC_TIME_CFG0_RUN        0x06183D2E */
 136 #define CONFIG_SYS_MDDRC_TIME_CFG0_RUN  0x030C3D2E
 137
 138 #define CONFIG_SYS_MICRON_NOP           0x01380000
 139 #define CONFIG_SYS_MICRON_PCHG_ALL      0x01100400
 140 #define CONFIG_SYS_MICRON_EM2           0x01020000
 141 #define CONFIG_SYS_MICRON_EM3           0x01030000
 142 #define CONFIG_SYS_MICRON_EN_DLL        0x01010000
 143 #define CONFIG_SYS_MICRON_RFSH          0x01080000
 144 #define CONFIG_SYS_MICRON_INIT_DEV_OP   0x01000432
 145 #define CONFIG_SYS_MICRON_OCD_DEFAULT   0x01010780
 146
 147 /* DDR Priority Manager Configuration */
 148 #define CONFIG_SYS_MDDRCGRP_PM_CFG1     0x00077777
 149 #define CONFIG_SYS_MDDRCGRP_PM_CFG2     0x00000000
 150 #define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG  0x00000001
 151 #define CONFIG_SYS_MDDRCGRP_LUT0_MU     0xFFEEDDCC
 152 #define CONFIG_SYS_MDDRCGRP_LUT0_ML     0xBBAAAAAA
 153 #define CONFIG_SYS_MDDRCGRP_LUT1_MU     0x66666666
 154 #define CONFIG_SYS_MDDRCGRP_LUT1_ML     0x55555555
 155 #define CONFIG_SYS_MDDRCGRP_LUT2_MU     0x44444444
 156 #define CONFIG_SYS_MDDRCGRP_LUT2_ML     0x44444444
 157 #define CONFIG_SYS_MDDRCGRP_LUT3_MU     0x55555555
 158 #define CONFIG_SYS_MDDRCGRP_LUT3_ML     0x55555558
 159 #define CONFIG_SYS_MDDRCGRP_LUT4_MU     0x11111111
 160 #define CONFIG_SYS_MDDRCGRP_LUT4_ML     0x11111122
 161 #define CONFIG_SYS_MDDRCGRP_LUT0_AU     0xaaaaaaaa
 162 #define CONFIG_SYS_MDDRCGRP_LUT0_AL     0xaaaaaaaa
 163 #define CONFIG_SYS_MDDRCGRP_LUT1_AU     0x66666666
 164 #define CONFIG_SYS_MDDRCGRP_LUT1_AL     0x66666666
 165 #define CONFIG_SYS_MDDRCGRP_LUT2_AU     0x11111111
 166 #define CONFIG_SYS_MDDRCGRP_LUT2_AL     0x11111111
 167 #define CONFIG_SYS_MDDRCGRP_LUT3_AU     0x11111111
 168 #define CONFIG_SYS_MDDRCGRP_LUT3_AL     0x11111111
 169 #define CONFIG_SYS_MDDRCGRP_LUT4_AU     0x11111111
 170 #define CONFIG_SYS_MDDRCGRP_LUT4_AL     0x11111111
 171
 172 /*
 173  * NOR FLASH on the Local Bus
 174  */
 175 #define CONFIG_SYS_FLASH_CFI                            /* use the CFI code */
 176 #define CONFIG_FLASH_CFI_DRIVER                         /* use the CFI driver */
 177 #define CONFIG_SYS_FLASH_BASE           0xF8000000      /* start of FLASH */
 178 #define CONFIG_SYS_FLASH_SIZE           0x08000000      /* max flash size */
 179
 180 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 181 #define CONFIG_SYS_MAX_FLASH_BANKS      1               /* number of banks */
 182 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE}
 183 #define CONFIG_SYS_MAX_FLASH_SECT       1024            /* max sectors */
 184
 185 #undef CONFIG_SYS_FLASH_CHECKSUM
 186
 187 #define CONFIG_SYS_SRAM_BASE            0x30000000
 188 #define CONFIG_SYS_SRAM_SIZE            0x00020000      /* 128 KB */
 189
 190 #define CONFIG_SYS_ARIA_SRAM_BASE       0x30020000
 191 #define CONFIG_SYS_ARIA_SRAM_SIZE       0x20000         /* 128 KB */
 192
 193 #define CONFIG_SYS_ARIA_FPGA_BASE       (CONFIG_SYS_ARIA_SRAM_BASE + \
 194                                          CONFIG_SYS_ARIA_SRAM_SIZE)
 195 #define CONFIG_SYS_ARIA_FPGA_SIZE       0x20000         /* 128 KB */
 196
 197 #define CONFIG_SYS_CS0_CFG              0x05059150
 198 #define CONFIG_SYS_CS2_CFG              (       (5 << 24) | \
 199                                                 (5 << 16) | \
 200                                                 (1 << 15) | \
 201                                                 (0 << 14) | \
 202                                                 (0 << 13) | \
 203                                                 (1 << 12) | \
 204                                                 (0 << 10) | \
 205                                                 (3 <<  8) | /* 32 bit */ \
 206                                                 (0 <<  7) | \
 207                                                 (1 <<  6) | \
 208                                                 (1 <<  4) | \
 209                                                 (0 <<  3) | \
 210                                                 (0 <<  2) | \
 211                                                 (0 <<  1) | \
 212                                                 (0 <<  0)   \
 213                                         )
 214 #define CONFIG_SYS_CS6_CFG              0x05059150
 215
 216 /* Use alternative CS timing for CS0 and CS2 */
 217 #define CONFIG_SYS_CS_ALETIMING 0x00000005
 218
 219 /* Use SRAM for initial stack */
 220 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_SRAM_BASE
 221 #define CONFIG_SYS_INIT_RAM_END         CONFIG_SYS_SRAM_SIZE
 222
 223 #define CONFIG_SYS_GBL_DATA_SIZE        0x100
 224 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - \
 225                                          CONFIG_SYS_GBL_DATA_SIZE)
 226 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 227
 228 #define CONFIG_SYS_MONITOR_BASE         TEXT_BASE
 229 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024)
 230
 231 #ifdef  CONFIG_FSL_DIU_FB
 232 #define CONFIG_SYS_MALLOC_LEN           (6 * 1024 * 1024)
 233 #else
 234 #define CONFIG_SYS_MALLOC_LEN           (512 * 1024)
 235 #endif
 236
 237 /* FPGA */
 238 #define CONFIG_ARIA_FPGA                1
 239
 240 /*
 241  * Serial Port
 242  */
 243 #define CONFIG_CONS_INDEX               1
 244 #undef CONFIG_SERIAL_SOFTWARE_FIFO
 245
 246 /*
 247  * Serial console configuration
 248  */
 249 #define CONFIG_PSC_CONSOLE              3       /* console on PSC3 */
 250 #if CONFIG_PSC_CONSOLE != 3
 251 #error CONFIG_PSC_CONSOLE must be 3
 252 #endif
 253
 254 #define CONFIG_BAUDRATE                 115200  /* ... at 115200 bps */
 255 #define CONFIG_SYS_BAUDRATE_TABLE  \
 256         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 257
 258 #define CONSOLE_FIFO_TX_SIZE            FIFOC_PSC3_TX_SIZE
 259 #define CONSOLE_FIFO_TX_ADDR            FIFOC_PSC3_TX_ADDR
 260 #define CONSOLE_FIFO_RX_SIZE            FIFOC_PSC3_RX_SIZE
 261 #define CONSOLE_FIFO_RX_ADDR            FIFOC_PSC3_RX_ADDR
 262
 263 #define CONFIG_CMDLINE_EDITING          1       /* command line history */
 264 /* Use the HUSH parser */
 265 #define CONFIG_SYS_HUSH_PARSER
 266 #ifdef  CONFIG_SYS_HUSH_PARSER
 267 #define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
 268 #endif
 269
 270 /*
 271  * PCI
 272  */
 273 #ifdef CONFIG_PCI
 274
 275 #define CONFIG_SYS_PCI_MEM_BASE         0xA0000000
 276 #define CONFIG_SYS_PCI_MEM_PHYS         CONFIG_SYS_PCI_MEM_BASE
 277 #define CONFIG_SYS_PCI_MEM_SIZE         0x10000000      /* 256M */
 278 #define CONFIG_SYS_PCI_MMIO_BASE        (CONFIG_SYS_PCI_MEM_BASE + \
 279                                          CONFIG_SYS_PCI_MEM_SIZE)
 280 #define CONFIG_SYS_PCI_MMIO_PHYS        CONFIG_SYS_PCI_MMIO_BASE
 281 #define CONFIG_SYS_PCI_MMIO_SIZE        0x10000000      /* 256M */
 282 #define CONFIG_SYS_PCI_IO_BASE          0x00000000
 283 #define CONFIG_SYS_PCI_IO_PHYS          0x84000000
 284 #define CONFIG_SYS_PCI_IO_SIZE          0x01000000      /* 16M */
 285
 286 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 287
 288 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 289
 290 #endif
 291
 292 /* I2C */
 293 #define CONFIG_HARD_I2C                 /* I2C with hardware support */
 294 #undef CONFIG_SOFT_I2C                  /* so disable bit-banged I2C */
 295 #define CONFIG_I2C_MULTI_BUS
 296 #define CONFIG_I2C_CMD_TREE
 297
 298 /* I2C speed and slave address */
 299 #define CONFIG_SYS_I2C_SPEED            100000
 300 #define CONFIG_SYS_I2C_SLAVE            0x7F
 301 #if 0
 302 #define CONFIG_SYS_I2C_NOPROBES {{0,0x69}}      /* Don't probe these addrs */
 303 #endif
 304
 305 /*
 306  * IIM - IC Identification Module
 307  */
 308 #undef CONFIG_IIM
 309
 310 /*
 311  * EEPROM configuration for Atmel AT24C32A-10TQ-2.7:
 312  * 16-bit addresses, 10ms write delay, 32-Byte Page Write Mode
 313  */
 314 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2
 315 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x50
 316 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10
 317 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       5
 318
 319 /*
 320  * Ethernet configuration
 321  */
 322 #define CONFIG_MPC512x_FEC              1
 323 #define CONFIG_NET_MULTI
 324 #define CONFIG_PHY_ADDR                 0x17
 325 #define CONFIG_MII                      1       /* MII PHY management */
 326 #define CONFIG_FEC_AN_TIMEOUT           1
 327 #define CONFIG_HAS_ETH0
 328
 329 /*
 330  * Environment
 331  */
 332 #define CONFIG_ENV_IS_IN_FLASH  1
 333 /* This has to be a multiple of the flash sector size */
 334 #define CONFIG_ENV_ADDR                 (CONFIG_SYS_MONITOR_BASE + \
 335                                          CONFIG_SYS_MONITOR_LEN)
 336 #define CONFIG_ENV_SIZE                 0x2000
 337 #define CONFIG_ENV_SECT_SIZE            0x20000 /* one sector (256K) */
 338
 339 /* Address and size of Redundant Environment Sector     */
 340 #define CONFIG_ENV_ADDR_REDUND          (CONFIG_ENV_ADDR + \
 341                                          CONFIG_ENV_SECT_SIZE)
 342 #define CONFIG_ENV_SIZE_REDUND          (CONFIG_ENV_SIZE)
 343
 344 #define CONFIG_LOADS_ECHO               1
 345 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1
 346
 347 #include <config_cmd_default.h>
 348
 349 #define CONFIG_CMD_ASKENV
 350 #define CONFIG_CMD_DHCP
 351 #define CONFIG_CMD_EEPROM
 352 #undef CONFIG_CMD_FUSE
 353 #define CONFIG_CMD_I2C
 354 #undef CONFIG_CMD_IDE
 355 #define CONFIG_CMD_MII
 356 #define CONFIG_CMD_NFS
 357 #define CONFIG_CMD_PING
 358 #define CONFIG_CMD_REGINFO
 359
 360 #if defined(CONFIG_PCI)
 361 #define CONFIG_CMD_PCI
 362 #endif
 363
 364 #if defined(CONFIG_CMD_IDE)
 365 #define CONFIG_DOS_PARTITION
 366 #define CONFIG_MAC_PARTITION
 367 #define CONFIG_ISO_PARTITION
 368 #endif /* defined(CONFIG_CMD_IDE) */
 369
 370 /*
 371  * Watchdog timeout = CONFIG_SYS_WATCHDOG_VALUE * 65536 / IPS clock.
 372  * For example, when IPS is set to 66MHz and CONFIG_SYS_WATCHDOG_VALUE
 373  * is set to 0xFFFF, watchdog timeouts after about 64s. For details
 374  * refer to chapter 36 of the MPC5121e Reference Manual.
 375  */
 376 /* #define CONFIG_WATCHDOG */           /* enable watchdog */
 377 #define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF
 378
 379  /*
 380  * Miscellaneous configurable options
 381  */
 382 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 383 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 384 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
 385
 386 #ifdef CONFIG_CMD_KGDB
 387 # define CONFIG_SYS_CBSIZE      1024            /* Console I/O Buffer Size */
 388 #else
 389 # define CONFIG_SYS_CBSIZE      256             /* Console I/O Buffer Size */
 390 #endif
 391
 392 /* Print Buffer Size */
 393 #define CONFIG_SYS_PBSIZE       (CONFIG_SYS_CBSIZE + \
 394                                  sizeof(CONFIG_SYS_PROMPT) + 16)
 395 /* max number of command args */
 396 #define CONFIG_SYS_MAXARGS      32
 397 /* Boot Argument Buffer Size */
 398 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 399
 400 #define CONFIG_SYS_HZ           1000
 401
 402 /*
 403  * For booting Linux, the board info and command line data
 404  * have to be in the first 8 MB of memory, since this is
 405  * the maximum mapped by the Linux kernel during initialization.
 406  */
 407 #define CONFIG_SYS_BOOTMAPSZ    (8 << 20)
 408
 409 /* Cache Configuration */
 410 #define CONFIG_SYS_DCACHE_SIZE          32768
 411 #define CONFIG_SYS_CACHELINE_SIZE       32
 412 #ifdef CONFIG_CMD_KGDB
 413 #define CONFIG_SYS_CACHELINE_SHIFT      5       /* log base 2 of 32 */
 414 #endif
 415
 416 #define CONFIG_SYS_HID0_INIT            0x000000000
 417 #define CONFIG_SYS_HID0_FINAL           (HID0_ENABLE_MACHINE_CHECK | \
 418                                          HID0_ICE)
 419 #define CONFIG_SYS_HID2 HID2_HBE
 420
 421 #define CONFIG_HIGH_BATS                1       /* High BATs supported */
 422
 423 /*
 424  * Internal Definitions
 425  *
 426  * Boot Flags
 427  */
 428 #define BOOTFLAG_COLD                   0x01
 429 #define BOOTFLAG_WARM                   0x02
 430
 431 #ifdef CONFIG_CMD_KGDB
 432 #define CONFIG_KGDB_BAUDRATE            230400  /* speed of kgdb serial port */
 433 #define CONFIG_KGDB_SER_INDEX           2       /* which serial port to use */
 434 #endif
 435
 436 /*
 437  * Environment Configuration
 438  */
 439 #define CONFIG_ENV_OVERWRITE
 440 #define CONFIG_TIMESTAMP
 441
 442 #define CONFIG_HOSTNAME                 aria
 443 #define CONFIG_BOOTFILE                 aria/uImage
 444 #define CONFIG_ROOTPATH                 /opt/eldk/ppc_6xx
 445
 446 #define CONFIG_LOADADDR                 400000  /* default load addr */
 447
 448 #define CONFIG_BOOTDELAY        5       /* -1 disables auto-boot */
 449 #undef  CONFIG_BOOTARGS                 /* the boot command will set bootargs */
 450
 451 #define CONFIG_BAUDRATE         115200
 452
 453 #define CONFIG_PREBOOT  "echo;" \
 454         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
 455         "echo"
 456
 457 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 458         "u-boot_addr_r=200000\0"                                        \
 459         "kernel_addr_r=600000\0"                                        \
 460         "fdt_addr_r=880000\0"                                           \
 461         "ramdisk_addr_r=900000\0"                                       \
 462         "u-boot_addr=FFF00000\0"                                        \
 463         "kernel_addr=FFC40000\0"                                        \
 464         "fdt_addr=FFEC0000\0"                                           \
 465         "ramdisk_addr=FC040000\0"                                       \
 466         "ramdiskfile=aria/uRamdisk\0"                           \
 467         "u-boot=aria/u-boot.bin\0"                                      \
 468         "fdtfile=aria/aria.dtb\0"                                       \
 469         "netdev=eth0\0"                                                 \
 470         "consdev=ttyPSC0\0"                                             \
 471         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 472                 "nfsroot=${serverip}:${rootpath}\0"                     \
 473         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 474         "addip=setenv bootargs ${bootargs} "                            \
 475                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 476                 ":${hostname}:${netdev}:off panic=1\0"                  \
 477         "addtty=setenv bootargs ${bootargs} "                           \
 478                 "console=${consdev},${baudrate}\0"                      \
 479         "flash_nfs=run nfsargs addip addtty;"                           \
 480                 "bootm ${kernel_addr} - ${fdt_addr}\0"                  \
 481         "flash_self=run ramargs addip addtty;"                          \
 482                 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"    \
 483         "net_nfs=tftp ${kernel_addr_r} ${bootfile};"                    \
 484                 "tftp ${fdt_addr_r} ${fdtfile};"                        \
 485                 "run nfsargs addip addtty;"                             \
 486                 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0"              \
 487         "net_self=tftp ${kernel_addr_r} ${bootfile};"                   \
 488                 "tftp ${ramdisk_addr_r} ${ramdiskfile};"                \
 489                 "tftp ${fdt_addr_r} ${fdtfile};"                        \
 490                 "run ramargs addip addtty;"                             \
 491                 "bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\
 492         "load=tftp ${u-boot_addr_r} ${u-boot}\0"                        \
 493         "update=protect off ${u-boot_addr} +${filesize};"               \
 494                 "era ${u-boot_addr} +${filesize};"                      \
 495                 "cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0"    \
 496         "upd=run load update\0"                                         \
 497         ""
 498
 499 #define CONFIG_BOOTCOMMAND      "run flash_self"
 500
 501 #define CONFIG_OF_LIBFDT        1
 502 #define CONFIG_OF_BOARD_SETUP   1
 503 #define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES      1
 504
 505 #define OF_CPU                  "PowerPC,5121@0"
 506 #define OF_SOC_COMPAT           "fsl,mpc5121-immr"
 507 #define OF_TBCLK                (bd->bi_busfreq / 4)
 508 #define OF_STDOUT_PATH          "/soc@80000000/serial@11300"
 509
 510 /*-----------------------------------------------------------------------
 511  * IDE/ATA stuff
 512  *-----------------------------------------------------------------------
 513  */
 514
 515 #undef  CONFIG_IDE_8xx_PCCARD           /* Use IDE with PC Card Adapter */
 516 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 517 #undef  CONFIG_IDE_LED                  /* LED   for IDE not supported  */
 518
 519 #define CONFIG_IDE_RESET                /* reset for IDE supported      */
 520 #define CONFIG_IDE_PREINIT
 521
 522 #define CONFIG_SYS_IDE_MAXBUS           1       /* 1 IDE bus            */
 523 #define CONFIG_SYS_IDE_MAXDEVICE        2       /* 1 drive per IDE bus  */
 524
 525 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 526 #define CONFIG_SYS_ATA_BASE_ADDR        get_pata_base()
 527
 528 /* Offset for data I/O                  RefMan MPC5121EE Table 28-10    */
 529 #define CONFIG_SYS_ATA_DATA_OFFSET      (0x00A0)
 530
 531 /* Offset for normal register accesses  */
 532 #define CONFIG_SYS_ATA_REG_OFFSET       (CONFIG_SYS_ATA_DATA_OFFSET)
 533
 534 /* Offset for alternate registers       RefMan MPC5121EE Table 28-23    */
 535 #define CONFIG_SYS_ATA_ALT_OFFSET       (0x00D8)
 536
 537 /* Interval between registers   */
 538 #define CONFIG_SYS_ATA_STRIDE           4
 539
 540 #define ATA_BASE_ADDR                   get_pata_base()
 541
 542 /*
 543  * Control register bit definitions
 544  */
 545 #define FSL_ATA_CTRL_FIFO_RST_B         0x80000000
 546 #define FSL_ATA_CTRL_ATA_RST_B          0x40000000
 547 #define FSL_ATA_CTRL_FIFO_TX_EN         0x20000000
 548 #define FSL_ATA_CTRL_FIFO_RCV_EN        0x10000000
 549 #define FSL_ATA_CTRL_DMA_PENDING        0x08000000
 550 #define FSL_ATA_CTRL_DMA_ULTRA          0x04000000
 551 #define FSL_ATA_CTRL_DMA_WRITE          0x02000000
 552 #define FSL_ATA_CTRL_IORDY_EN           0x01000000
 553
 554 #endif  /* __CONFIG_H */