1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2010 Andreas Bießmann <biessmann.devel@googlemail.com>
5 * based on previous work by
7 * Ulf Samuelsson <ulf@atmel.com>
8 * Rick Bronson <rick@efn.org>
10 * Configuration settings for the AT91RM9200EK board.
13 #ifndef __AT91RM9200EK_CONFIG_H__
14 #define __AT91RM9200EK_CONFIG_H__
16 #include <linux/sizes.h>
19 * set some initial configurations depending on configure target
21 * at91rm9200ek_config -> boot from 0x0 in NOR Flash at CS0
22 * at91rm9200ek_ram_config -> continue booting from 0x20100000 in RAM; lowlevel
23 * initialisation was done by some preloader
26 #define CONFIG_SKIP_LOWLEVEL_INIT
30 * AT91C_XTAL_CLOCK is the frequency of external xtal in hertz
31 * AT91C_MAIN_CLOCK is the frequency of PLLA output
32 * AT91C_MASTER_CLOCK is the peripherial clock
33 * CONFIG_SYS_HZ_CLOCK is the value for CCR in tc0 (divider 2 is implicitely
34 * set in arch/arm/cpu/arm920t/at91/timer.c)
35 * CONFIG_SYS_HZ is the tick rate for timer tc0
37 #define AT91C_XTAL_CLOCK 18432000
38 #define CONFIG_SYS_AT91_SLOW_CLOCK 32768
39 #define AT91C_MAIN_CLOCK ((AT91C_XTAL_CLOCK / 4) * 39)
40 #define AT91C_MASTER_CLOCK (AT91C_MAIN_CLOCK / 3 )
41 #define CONFIG_SYS_HZ_CLOCK (AT91C_MASTER_CLOCK / 2)
43 /* CPU configuration */
44 #define CONFIG_AT91RM9200
45 #define CONFIG_AT91RM9200EK
48 #include <asm/hardware.h> /* needed for port definitions */
50 #define CONFIG_CMDLINE_TAG
51 #define CONFIG_SETUP_MEMORY_TAGS
52 #define CONFIG_INITRD_TAG
55 * Memory Configuration
57 #define CONFIG_NR_DRAM_BANKS 1
58 #define CONFIG_SYS_SDRAM_BASE 0x20000000
59 #define CONFIG_SYS_SDRAM_SIZE SZ_32M
61 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
62 #define CONFIG_SYS_MEMTEST_END \
63 (CONFIG_SYS_MEMTEST_START + CONFIG_SYS_SDRAM_SIZE - SZ_256K)
68 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
69 #define CONFIG_SYS_USE_MAIN_OSCILLATOR
71 #define CONFIG_SYS_EBI_CFGR_VAL 0x00000000
72 #define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
75 #define CONFIG_SYS_PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */
76 #define CONFIG_SYS_PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
77 /* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */
78 #define CONFIG_SYS_MCKR_VAL 0x00000202
81 #define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
82 #define CONFIG_SYS_PIOC_BSR_VAL 0x00000000
83 #define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000
84 #define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=CONFIG_SYS_SDRAM */
85 #define CONFIG_SYS_SDRC_CR_VAL 0x2188c155 /* set up the CONFIG_SYS_SDRAM */
86 #define CONFIG_SYS_SDRAM CONFIG_SYS_SDRAM_BASE /* address of the SDRAM */
87 #define CONFIG_SYS_SDRAM1 (CONFIG_SYS_SDRAM_BASE+0x80)
88 #define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to CONFIG_SYS_SDRAM */
89 #define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */
90 #define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */
91 #define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
92 #define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */
93 #define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
94 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */
100 * Choose a USART for serial console
101 * CONFIG_DBGU is DBGU unit on J10
102 * CONFIG_USART1 is USART1 on J14
104 #define CONFIG_ATMEL_USART
105 #define CONFIG_USART_BASE ATMEL_BASE_DBGU
106 #define CONFIG_USART_ID 0/* ignored in arm */
109 * Command line configuration.
113 * Network Driver Setting
115 #define CONFIG_DRIVER_AT91EMAC
116 #define CONFIG_SYS_RX_ETH_BUFFER 16
123 #define CONFIG_FLASH_CFI_DRIVER
124 #define CONFIG_SYS_FLASH_CFI
125 #define CONFIG_SYS_FLASH_BASE 0x10000000
126 #define PHYS_FLASH_1 CONFIG_SYS_FLASH_BASE
127 #define PHYS_FLASH_SIZE SZ_8M
128 #define CONFIG_SYS_MAX_FLASH_BANKS 1
129 #define CONFIG_SYS_MAX_FLASH_SECT 256
130 #define CONFIG_SYS_FLASH_PROTECTION
135 #define CONFIG_USB_ATMEL 1
136 #define CONFIG_USB_ATMEL_CLK_SEL_PLLB
137 #define CONFIG_USB_OHCI_NEW 1
139 #define CONFIG_SYS_USB_OHCI_CPU_INIT 1
140 #define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_USB_HOST_BASE
141 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91rm9200"
142 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
145 * Environment Settings
151 #define CONFIG_ENV_ADDR \
152 (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
153 #define CONFIG_ENV_SIZE SZ_64K /* sectors are 64K here */
154 /* The following #defines are needed to get flash environment right */
155 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
156 #define CONFIG_SYS_MONITOR_LEN SZ_256K
162 /* default load address */
163 #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_16M
164 #define CONFIG_ENV_OVERWRITE
171 * Size of malloc() pool
173 #define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + SZ_128K, \
176 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_4K \
177 - GENERATED_GBL_DATA_SIZE)
179 #endif /* __AT91RM9200EK_CONFIG_H__ */