2 * Copyright (C) 2006 Atmel Corporation
4 * Configuration settings for the AVR32 Network Gateway
6 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/arch/hardware.h>
14 #define CONFIG_AT32AP7000
15 #define CONFIG_ATNGW100
17 #define CONFIG_BOARD_EARLY_INIT_R
20 * Set up the PLL to run at 140 MHz, the CPU to run at the PLL
21 * frequency, the HSB and PBB busses to run at 1/2 the PLL frequency
22 * and the PBA bus to run at 1/4 the PLL frequency.
25 #define CONFIG_SYS_POWER_MANAGER
26 #define CONFIG_SYS_OSC0_HZ 20000000
27 #define CONFIG_SYS_PLL0_DIV 1
28 #define CONFIG_SYS_PLL0_MUL 7
29 #define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16
30 #define CONFIG_SYS_CLKDIV_CPU 0
31 #define CONFIG_SYS_CLKDIV_HSB 1
32 #define CONFIG_SYS_CLKDIV_PBA 2
33 #define CONFIG_SYS_CLKDIV_PBB 1
35 /* Reserve VM regions for SDRAM and NOR flash */
36 #define CONFIG_SYS_NR_VM_REGIONS 2
39 * The PLLOPT register controls the PLL like this:
43 * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
45 #define CONFIG_SYS_PLL0_OPT 0x04
47 #define CONFIG_USART_BASE ATMEL_BASE_USART1
48 #define CONFIG_USART_ID 1
49 /* User serviceable stuff */
50 #define CONFIG_DOS_PARTITION
52 #define CONFIG_CMDLINE_TAG
53 #define CONFIG_SETUP_MEMORY_TAGS
54 #define CONFIG_INITRD_TAG
56 #define CONFIG_STACKSIZE (2048)
58 #define CONFIG_BAUDRATE 115200
59 #define CONFIG_BOOTARGS \
60 "console=ttyS0 root=/dev/mtdblock1 rootfstype=jffs2"
61 #define CONFIG_BOOTCOMMAND \
66 * After booting the board for the first time, new ethernet addresses
67 * should be generated and assigned to the environment variables
68 * "ethaddr" and "eth1addr". This is normally done during production.
70 #define CONFIG_OVERWRITE_ETHADDR_ONCE
75 #define CONFIG_BOOTP_SUBNETMASK
76 #define CONFIG_BOOTP_GATEWAY
79 * Command line configuration.
81 #define CONFIG_CMD_JFFS2
83 #define CONFIG_ATMEL_USART
85 #define CONFIG_PORTMUX_PIO
86 #define CONFIG_SYS_NR_PIOS 5
87 #define CONFIG_SYS_HSDRAMC
88 #define CONFIG_GENERIC_ATMEL_MCI
89 #define CONFIG_GENERIC_MMC
90 #define CONFIG_ATMEL_SPI
92 #define CONFIG_SYS_DCACHE_LINESZ 32
93 #define CONFIG_SYS_ICACHE_LINESZ 32
95 #define CONFIG_NR_DRAM_BANKS 1
97 #define CONFIG_SYS_FLASH_CFI
98 #define CONFIG_FLASH_CFI_DRIVER
100 #define CONFIG_SYS_FLASH_BASE 0x00000000
101 #define CONFIG_SYS_FLASH_SIZE 0x800000
102 #define CONFIG_SYS_MAX_FLASH_BANKS 1
103 #define CONFIG_SYS_MAX_FLASH_SECT 135
105 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
106 #define CONFIG_SYS_TEXT_BASE 0x00000000
108 #define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE
109 #define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE
110 #define CONFIG_SYS_SDRAM_BASE EBI_SDRAM_BASE
112 #define CONFIG_ENV_IS_IN_FLASH
113 #define CONFIG_ENV_SIZE 65536
114 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE)
116 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE)
118 #define CONFIG_SYS_MALLOC_LEN (256*1024)
120 /* Allow 4MB for the kernel run-time image */
121 #define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000)
122 #define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024)
124 /* Other configuration settings that shouldn't have to change all that often */
125 #define CONFIG_SYS_CBSIZE 256
126 #define CONFIG_SYS_MAXARGS 16
127 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
128 #define CONFIG_SYS_LONGHELP
130 #define CONFIG_SYS_MEMTEST_START EBI_SDRAM_BASE
131 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x1f00000)
133 #define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
135 #endif /* __CONFIG_H */