2 * Copyright (C) 2005-2006 Atmel Corporation
4 * Configuration settings for the ATSTK1002 CPU daughterboard
6 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/arch/hardware.h>
14 #define CONFIG_AT32AP7000
15 #define CONFIG_ATSTK1002
16 #define CONFIG_ATSTK1000
19 * Set up the PLL to run at 140 MHz, the CPU to run at the PLL
20 * frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the
22 * (CONFIG_SYS_OSC0_HZ * CONFIG_SYS_PLL0_MUL) / CONFIG_SYS_PLL0_DIV = PLL MHz
25 #define CONFIG_SYS_POWER_MANAGER
26 #define CONFIG_SYS_OSC0_HZ 20000000
27 #define CONFIG_SYS_PLL0_DIV 1
28 #define CONFIG_SYS_PLL0_MUL 7
29 #define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16
31 * Set the CPU running at:
32 * PLL / (2^CONFIG_SYS_CLKDIV_CPU) = CPU MHz
34 #define CONFIG_SYS_CLKDIV_CPU 0
36 * Set the HSB running at:
37 * PLL / (2^CONFIG_SYS_CLKDIV_HSB) = HSB MHz
39 #define CONFIG_SYS_CLKDIV_HSB 1
41 * Set the PBA running at:
42 * PLL / (2^CONFIG_SYS_CLKDIV_PBA) = PBA MHz
44 #define CONFIG_SYS_CLKDIV_PBA 2
46 * Set the PBB running at:
47 * PLL / (2^CONFIG_SYS_CLKDIV_PBB) = PBB MHz
49 #define CONFIG_SYS_CLKDIV_PBB 1
51 /* Reserve VM regions for SDRAM and NOR flash */
52 #define CONFIG_SYS_NR_VM_REGIONS 2
55 * The PLLOPT register controls the PLL like this:
59 * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
61 #define CONFIG_SYS_PLL0_OPT 0x04
63 #define CONFIG_USART_BASE ATMEL_BASE_USART1
64 #define CONFIG_USART_ID 1
66 /* User serviceable stuff */
68 #define CONFIG_CMDLINE_TAG
69 #define CONFIG_SETUP_MEMORY_TAGS
70 #define CONFIG_INITRD_TAG
72 #define CONFIG_BOOTARGS \
73 "console=ttyS0 root=/dev/mmcblk0p1 fbmem=600k rootwait=1"
75 #define CONFIG_BOOTCOMMAND \
76 "fsload; bootm $(fileaddr)"
80 * After booting the board for the first time, new ethernet addresses
81 * should be generated and assigned to the environment variables
82 * "ethaddr" and "eth1addr". This is normally done during production.
84 #define CONFIG_OVERWRITE_ETHADDR_ONCE
89 #define CONFIG_BOOTP_SUBNETMASK
90 #define CONFIG_BOOTP_GATEWAY
93 #define CONFIG_BOARD_EARLY_INIT_R
96 * Command line configuration.
98 #define CONFIG_CMD_JFFS2
100 #define CONFIG_ATMEL_USART
102 #define CONFIG_PORTMUX_PIO
103 #define CONFIG_SYS_NR_PIOS 5
104 #define CONFIG_SYS_HSDRAMC
105 #define CONFIG_GENERIC_ATMEL_MCI
107 #define CONFIG_SYS_DCACHE_LINESZ 32
108 #define CONFIG_SYS_ICACHE_LINESZ 32
110 #define CONFIG_NR_DRAM_BANKS 1
112 #define CONFIG_SYS_FLASH_CFI
113 #define CONFIG_FLASH_CFI_DRIVER
115 #define CONFIG_SYS_FLASH_BASE 0x00000000
116 #define CONFIG_SYS_FLASH_SIZE 0x800000
117 #define CONFIG_SYS_MAX_FLASH_BANKS 1
118 #define CONFIG_SYS_MAX_FLASH_SECT 135
120 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
121 #define CONFIG_SYS_TEXT_BASE 0x00000000
123 #define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE
124 #define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE
125 #define CONFIG_SYS_SDRAM_BASE EBI_SDRAM_BASE
127 #define CONFIG_ENV_IS_IN_FLASH
128 #define CONFIG_ENV_SIZE 65536
129 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE)
131 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE)
133 #define CONFIG_SYS_MALLOC_LEN (256*1024)
135 /* Allow 4MB for the kernel run-time image */
136 #define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000)
137 #define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024)
139 /* Other configuration settings that shouldn't have to change all that often */
140 #define CONFIG_SYS_CBSIZE 256
141 #define CONFIG_SYS_MAXARGS 16
142 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
143 #define CONFIG_SYS_LONGHELP
145 #define CONFIG_SYS_MEMTEST_START EBI_SDRAM_BASE
146 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x700000)
147 #define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
149 #endif /* __CONFIG_H */