2 * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef _CONFIG_AXS101_H_
8 #define _CONFIG_AXS101_H_
13 #define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ
15 #define ARC_FPGA_PERIPHERAL_BASE 0xE0000000
16 #define ARC_APB_PERIPHERAL_BASE 0xF0000000
17 #define ARC_DWMMC_BASE (ARC_FPGA_PERIPHERAL_BASE + 0x15000)
18 #define ARC_DWGMAC_BASE (ARC_FPGA_PERIPHERAL_BASE + 0x18000)
21 * Memory configuration
23 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
25 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
26 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
27 #define CONFIG_SYS_SDRAM_SIZE 0x20000000 /* 512 Mb */
29 #define CONFIG_SYS_INIT_SP_ADDR \
30 (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
32 #define CONFIG_SYS_MALLOC_LEN 0x200000 /* 2 MB */
33 #define CONFIG_SYS_BOOTM_LEN 0x2000000 /* 32 MB */
34 #define CONFIG_SYS_LOAD_ADDR 0x82000000
37 * NAND Flash configuration
39 #define CONFIG_SYS_NO_FLASH
40 #define CONFIG_SYS_NAND_BASE (ARC_FPGA_PERIPHERAL_BASE + 0x16000)
41 #define CONFIG_SYS_MAX_NAND_DEVICE 1
46 * CONFIG_CONS_INDEX = 1 - Debug UART
47 * CONFIG_CONS_INDEX = 4 - FPGA UART connected to FTDI/USB
49 #define CONFIG_CONS_INDEX 4
50 #define CONFIG_SYS_NS16550
51 #define CONFIG_SYS_NS16550_SERIAL
52 #define CONFIG_SYS_NS16550_REG_SIZE -4
53 #if (CONFIG_CONS_INDEX == 1)
55 # define CONFIG_SYS_NS16550_CLK 33333000
57 /* FPGA UARTs use different clock */
58 # define CONFIG_SYS_NS16550_CLK 33333333
60 #define CONFIG_SYS_NS16550_COM1 (ARC_APB_PERIPHERAL_BASE + 0x5000)
61 #define CONFIG_SYS_NS16550_COM2 (ARC_FPGA_PERIPHERAL_BASE + 0x20000)
62 #define CONFIG_SYS_NS16550_COM3 (ARC_FPGA_PERIPHERAL_BASE + 0x21000)
63 #define CONFIG_SYS_NS16550_COM4 (ARC_FPGA_PERIPHERAL_BASE + 0x22000)
64 #define CONFIG_SYS_NS16550_MEM32
66 #define CONFIG_BAUDRATE 115200
70 #define CONFIG_SYS_I2C
71 #define CONFIG_SYS_I2C_DW
72 #define CONFIG_I2C_ENV_EEPROM_BUS 2
73 #define CONFIG_SYS_I2C_SPEED 100000
74 #define CONFIG_SYS_I2C_SPEED1 100000
75 #define CONFIG_SYS_I2C_SPEED2 100000
76 #define CONFIG_SYS_I2C_SLAVE 0
77 #define CONFIG_SYS_I2C_SLAVE1 0
78 #define CONFIG_SYS_I2C_SLAVE2 0
79 #define CONFIG_SYS_I2C_BASE 0xE001D000
80 #define CONFIG_SYS_I2C_BASE1 0xE001E000
81 #define CONFIG_SYS_I2C_BASE2 0xE001F000
82 #define CONFIG_SYS_I2C_BUS_MAX 3
86 * EEPROM configuration
88 #define CONFIG_SYS_I2C_MULTI_EEPROMS
89 #define CONFIG_SYS_I2C_EEPROM_ADDR (0xA8 >> 1)
90 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
91 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 1
92 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
93 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 64
96 * SD/MMC configuration
99 #define CONFIG_GENERIC_MMC
101 #define CONFIG_DOS_PARTITION
104 * Ethernet PHY configuration
106 #define CONFIG_PHYLIB
108 #define CONFIG_PHY_GIGE
111 * Ethernet configuration
113 #define CONFIG_DESIGNWARE_ETH
114 #define CONFIG_DW_AUTONEG
115 #define CONFIG_NET_MULTI
118 * Command line configuration
120 #include <config_cmd_default.h>
122 #define CONFIG_CMD_DHCP
123 #define CONFIG_CMD_EEPROM
124 #define CONFIG_CMD_ELF
125 #define CONFIG_CMD_FAT
126 #define CONFIG_CMD_I2C
127 #define CONFIG_CMD_MMC
128 #define CONFIG_CMD_NAND
129 #define CONFIG_CMD_PING
130 #define CONFIG_CMD_RARP
132 #define CONFIG_OF_LIBFDT
134 #define CONFIG_AUTO_COMPLETE
135 #define CONFIG_SYS_MAXARGS 16
138 * Environment settings
140 #define CONFIG_ENV_IS_IN_EEPROM
141 #define CONFIG_ENV_SIZE 0x00200 /* 512 bytes */
142 #define CONFIG_ENV_OFFSET 0
145 * Environment configuration
147 #define CONFIG_BOOTDELAY 3
148 #define CONFIG_BOOTFILE "uImage"
149 #define CONFIG_BOOTARGS "console=ttyS3,115200n8"
150 #define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
153 * Console configuration
155 #define CONFIG_SYS_LONGHELP
156 #define CONFIG_SYS_PROMPT "AXS# "
157 #define CONFIG_SYS_CBSIZE 256
158 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
159 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
160 sizeof(CONFIG_SYS_PROMPT) + 16)
163 * Misc utility configuration
165 #define CONFIG_BOUNCE_BUFFER
167 #endif /* _CONFIG_AXS101_H_ */