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[u-boot] / include / configs / balloon3.h
1 /*
2  * Balloon3 configuration file
3  *
4  * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
5  *
6  * This program is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU General Public License as
8  * published by the Free Software Foundation; either version 2 of
9  * the License, or (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14  * GNU General Public License for more details.
15  *
16  * You should have received a copy of the GNU General Public License
17  * along with this program; if not, write to the Free Software
18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
19  * MA 02111-1307 USA
20  */
21
22 #ifndef __CONFIG_H
23 #define __CONFIG_H
24
25 /*
26  * High Level Board Configuration Options
27  */
28 #define CONFIG_CPU_PXA27X               1       /* Marvell PXA270 CPU */
29 #define CONFIG_BALLOON3         1       /* Balloon3 board */
30
31 /*
32  * Environment settings
33  */
34 #define CONFIG_ENV_OVERWRITE
35 #define CONFIG_SYS_MALLOC_LEN           (128*1024)
36 #define CONFIG_ARCH_CPU_INIT
37 #define CONFIG_BOOTCOMMAND                                              \
38         "fpga load 0x0 0x50000 0x62638; "                               \
39         "if usb reset && fatload usb 0 0xa4000000 uImage; then "        \
40                 "bootm 0xa4000000; "                                    \
41         "fi; "                                                          \
42         "bootm 0xd0000;"
43 #define CONFIG_BOOTARGS                 "console=tty0 console=ttyS2,115200"
44 #define CONFIG_TIMESTAMP
45 #define CONFIG_BOOTDELAY                2       /* Autoboot delay */
46 #define CONFIG_CMDLINE_TAG
47 #define CONFIG_SETUP_MEMORY_TAGS
48 #define CONFIG_SYS_TEXT_BASE            0x0
49 #define CONFIG_LZMA                     /* LZMA compression support */
50
51 /*
52  * Serial Console Configuration
53  */
54 #define CONFIG_PXA_SERIAL
55 #define CONFIG_STUART                   1
56 #define CONFIG_BAUDRATE                 115200
57
58 /*
59  * Bootloader Components Configuration
60  */
61 #include <config_cmd_default.h>
62
63 #undef  CONFIG_CMD_NET
64 #undef  CONFIG_CMD_NFS
65 #undef  CONFIG_CMD_ENV
66 #undef  CONFIG_CMD_IMLS
67 #define CONFIG_CMD_USB
68 #define CONFIG_CMD_FPGA
69 #undef  CONFIG_LCD
70
71 /*
72  * KGDB
73  */
74 #ifdef  CONFIG_CMD_KGDB
75 #define CONFIG_KGDB_BAUDRATE            230400  /* kgdb serial port speed */
76 #define CONFIG_KGDB_SER_INDEX           2       /* which serial port to use */
77 #endif
78
79 /*
80  * HUSH Shell Configuration
81  */
82 #define CONFIG_SYS_HUSH_PARSER          1
83
84 #define CONFIG_SYS_LONGHELP
85 #ifdef  CONFIG_SYS_HUSH_PARSER
86 #define CONFIG_SYS_PROMPT               "$ "
87 #else
88 #define CONFIG_SYS_PROMPT               "=> "
89 #endif
90 #define CONFIG_SYS_CBSIZE               256
91 #define CONFIG_SYS_PBSIZE               \
92         (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
93 #define CONFIG_SYS_MAXARGS              16
94 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
95 #define CONFIG_SYS_DEVICE_NULLDEV       1
96
97 /*
98  * Clock Configuration
99  */
100 #undef  CONFIG_SYS_CLKS_IN_HZ
101 #define CONFIG_SYS_HZ                   3250000         /* Timer @ 3250000 Hz */
102 #define CONFIG_SYS_CPUSPEED             0x290           /* 520MHz */
103
104 /*
105  * Stack sizes
106  */
107 #define CONFIG_STACKSIZE                (128*1024)      /* regular stack */
108 #ifdef  CONFIG_USE_IRQ
109 #define CONFIG_STACKSIZE_IRQ            (4*1024)        /* IRQ stack */
110 #define CONFIG_STACKSIZE_FIQ            (4*1024)        /* FIQ stack */
111 #endif
112
113 /*
114  * DRAM Map
115  */
116 #define CONFIG_NR_DRAM_BANKS            3               /* 2 banks of DRAM */
117 #define PHYS_SDRAM_1                    0xa0000000      /* SDRAM Bank #1 */
118 #define PHYS_SDRAM_1_SIZE               0x08000000      /* 128 MB */
119 #define PHYS_SDRAM_2                    0xb0000000      /* SDRAM Bank #2 */
120 #define PHYS_SDRAM_2_SIZE               0x08000000      /* 128 MB */
121 #define PHYS_SDRAM_3                    0x80000000      /* SDRAM Bank #2 */
122 #define PHYS_SDRAM_3_SIZE               0x08000000      /* 128 MB */
123
124 #define CONFIG_SYS_DRAM_BASE            0xa0000000      /* CS0 */
125 #define CONFIG_SYS_DRAM_SIZE            0x18000000      /* 384 MB DRAM */
126
127 #define CONFIG_SYS_MEMTEST_START        0xa0400000      /* memtest works on */
128 #define CONFIG_SYS_MEMTEST_END          0xa0800000      /* 4 ... 8 MB in DRAM */
129
130 #define CONFIG_SYS_LOAD_ADDR            0xa1000000
131
132 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
133 #define CONFIG_SYS_INIT_SP_ADDR         \
134         (PHYS_SDRAM_1 + GENERATED_GBL_DATA_SIZE + 2048)
135
136 /*
137  * NOR FLASH
138  */
139 #ifdef  CONFIG_CMD_FLASH
140 #define PHYS_FLASH_1                    0x00000000      /* Flash Bank #1 */
141 #define PHYS_FLASH_SIZE                 0x00800000      /* 8 MB */
142 #define CONFIG_SYS_FLASH_BASE           PHYS_FLASH_1
143
144 #define CONFIG_SYS_FLASH_CFI
145 #define CONFIG_FLASH_CFI_DRIVER         1
146 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
147
148 #define CONFIG_SYS_MAX_FLASH_BANKS      1
149 #define CONFIG_SYS_MAX_FLASH_SECT       256
150
151 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE       1
152
153 #define CONFIG_SYS_FLASH_ERASE_TOUT     (2*CONFIG_SYS_HZ)
154 #define CONFIG_SYS_FLASH_WRITE_TOUT     (2*CONFIG_SYS_HZ)
155 #define CONFIG_SYS_FLASH_LOCK_TOUT      (2*CONFIG_SYS_HZ)
156 #define CONFIG_SYS_FLASH_UNLOCK_TOUT    (2*CONFIG_SYS_HZ)
157 #define CONFIG_SYS_FLASH_PROTECTION
158 #define CONFIG_ENV_IS_IN_FLASH
159 #else
160 #define CONFIG_SYS_NO_FLASH
161 #define CONFIG_SYS_ENV_IS_NOWHERE
162 #endif
163
164 #define CONFIG_SYS_MONITOR_BASE         0x000000
165 #define CONFIG_SYS_MONITOR_LEN          0x40000
166
167 #define CONFIG_ENV_SIZE                 0x2000
168 #define CONFIG_ENV_ADDR                 0x40000
169 #define CONFIG_ENV_SECT_SIZE            0x10000
170
171 /*
172  * GPIO settings
173  */
174 #define CONFIG_SYS_GPSR0_VAL    0x307dc7fd
175 #define CONFIG_SYS_GPSR1_VAL    0x03cffa4e
176 #define CONFIG_SYS_GPSR2_VAL    0x7131c000
177 #define CONFIG_SYS_GPSR3_VAL    0x01e1f3ff
178
179 #define CONFIG_SYS_GPCR0_VAL    0x0
180 #define CONFIG_SYS_GPCR1_VAL    0x0
181 #define CONFIG_SYS_GPCR2_VAL    0x0
182 #define CONFIG_SYS_GPCR3_VAL    0x0
183
184 #define CONFIG_SYS_GPDR0_VAL    0xc0f98e02
185 #define CONFIG_SYS_GPDR1_VAL    0xfcffa8b7
186 #define CONFIG_SYS_GPDR2_VAL    0x22e3ffff
187 #define CONFIG_SYS_GPDR3_VAL    0x000201fe
188
189 #define CONFIG_SYS_GAFR0_L_VAL  0x96c00000
190 #define CONFIG_SYS_GAFR0_U_VAL  0xa5e5459b
191 #define CONFIG_SYS_GAFR1_L_VAL  0x699b759a
192 #define CONFIG_SYS_GAFR1_U_VAL  0xaaa5a5aa
193 #define CONFIG_SYS_GAFR2_L_VAL  0xaaaaaaaa
194 #define CONFIG_SYS_GAFR2_U_VAL  0x01f9a6aa
195 #define CONFIG_SYS_GAFR3_L_VAL  0x54510003
196 #define CONFIG_SYS_GAFR3_U_VAL  0x00001599
197
198 #define CONFIG_SYS_PSSR_VAL     0x30
199
200 /*
201  * Clock settings
202  */
203 #define CONFIG_SYS_CKEN         0xffffffff
204 #define CONFIG_SYS_CCCR         0x00000290
205
206 /*
207  * Memory settings
208  */
209 #define CONFIG_SYS_MSC0_VAL     0x7ff07ff8
210 #define CONFIG_SYS_MSC1_VAL     0x7ff07ff0
211 #define CONFIG_SYS_MSC2_VAL     0x74a42491
212 #define CONFIG_SYS_MDCNFG_VAL   0x89d309d3
213 #define CONFIG_SYS_MDREFR_VAL   0x001d8018
214 #define CONFIG_SYS_MDMRS_VAL    0x00220022
215 #define CONFIG_SYS_FLYCNFG_VAL  0x00000000
216 #define CONFIG_SYS_SXCNFG_VAL   0x00000000
217 #define CONFIG_SYS_MEM_BUF_IMP  0x0f
218
219 /*
220  * PCMCIA and CF Interfaces
221  */
222 #define CONFIG_SYS_MECR_VAL     0x00000000
223 #define CONFIG_SYS_MCMEM0_VAL   0x00014307
224 #define CONFIG_SYS_MCMEM1_VAL   0x00014307
225 #define CONFIG_SYS_MCATT0_VAL   0x0001c787
226 #define CONFIG_SYS_MCATT1_VAL   0x0001c787
227 #define CONFIG_SYS_MCIO0_VAL    0x0001430f
228 #define CONFIG_SYS_MCIO1_VAL    0x0001430f
229
230 /*
231  * LCD
232  */
233 #ifdef  CONFIG_LCD
234 #define CONFIG_BALLOON3LCD
235 #define CONFIG_VIDEO_LOGO
236 #define CONFIG_CMD_BMP
237 #define CONFIG_SPLASH_SCREEN
238 #define CONFIG_SPLASH_SCREEN_ALIGN
239 #define CONFIG_VIDEO_BMP_GZIP
240 #define CONFIG_VIDEO_BMP_RLE8
241 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE  (2 << 20)
242 #endif
243
244 /*
245  * USB
246  */
247 #ifdef  CONFIG_CMD_USB
248 #define CONFIG_USB_OHCI_NEW
249 #define CONFIG_SYS_USB_OHCI_CPU_INIT
250 #define CONFIG_SYS_USB_OHCI_BOARD_INIT
251 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      2
252 #define CONFIG_SYS_USB_OHCI_REGS_BASE   0x4C000000
253 #define CONFIG_SYS_USB_OHCI_SLOT_NAME   "balloon3"
254 #define CONFIG_USB_STORAGE
255 #define CONFIG_DOS_PARTITION
256 #define CONFIG_CMD_FAT
257 #define CONFIG_CMD_EXT2
258 #endif
259
260 /*
261  * FPGA
262  */
263 #ifdef  CONFIG_CMD_FPGA
264 #define CONFIG_FPGA
265 #define CONFIG_FPGA_XILINX
266 #define CONFIG_FPGA_SPARTAN3
267 #define CONFIG_SYS_FPGA_PROG_FEEDBACK
268 #define CONFIG_SYS_FPGA_WAIT    1000
269 #define CONFIG_MAX_FPGA_DEVICES 1
270 #endif
271
272 #endif  /* __CONFIG_H */