2 * U-boot - Configuration file for BF533 STAMP board
5 #ifndef __CONFIG_BF533_STAMP_H__
6 #define __CONFIG_BF533_STAMP_H__
8 #include <asm/config-pre.h>
14 #define CONFIG_BFIN_CPU bf533-0.3
15 #define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
19 * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
20 * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
22 /* CONFIG_CLKIN_HZ is any value in Hz */
23 #define CONFIG_CLKIN_HZ 11059200
24 /* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
26 #define CONFIG_CLKIN_HALF 0
27 /* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
29 #define CONFIG_PLL_BYPASS 0
30 /* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
31 /* Values can range from 0-63 (where 0 means 64) */
32 #define CONFIG_VCO_MULT 45
33 /* CCLK_DIV controls the core clock divider */
34 /* Values can be 1, 2, 4, or 8 ONLY */
35 #define CONFIG_CCLK_DIV 1
36 /* SCLK_DIV controls the system clock divider */
37 /* Values can range from 1-15 */
38 #define CONFIG_SCLK_DIV 6 /* note: 1.2 boards can go faster */
43 #define CONFIG_MEM_ADD_WDTH 11
44 #define CONFIG_MEM_SIZE 128
46 #define CONFIG_EBIU_SDRRC_VAL 0x268
47 #define CONFIG_EBIU_SDGCTL_VAL 0x911109
49 #define CONFIG_EBIU_AMGCTL_VAL 0xFF
50 #define CONFIG_EBIU_AMBCTL0_VAL 0xBBC3BBC3
51 #define CONFIG_EBIU_AMBCTL1_VAL 0x99B39983
53 #define CONFIG_SYS_MONITOR_LEN (256 * 1024)
54 #define CONFIG_SYS_MALLOC_LEN (384 * 1024)
60 #define ADI_CMDS_NETWORK 1
61 #define CONFIG_SMC91111 1
62 #define CONFIG_SMC91111_BASE 0x20300300
63 #define SMC91111_EEPROM_INIT() \
65 bfin_write_FIO_DIR(bfin_read_FIO_DIR() | PF1 | PF0); \
66 bfin_write_FIO_FLAG_C(PF1); \
67 bfin_write_FIO_FLAG_S(PF0); \
70 #define CONFIG_HOSTNAME bf533-stamp
74 #define CONFIG_SYS_I2C
75 #define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
76 #define CONFIG_SYS_I2C_SOFT_SPEED 50000
77 #define CONFIG_SYS_I2C_SOFT_SLAVE 0
79 * Software (bit-bang) I2C driver configuration
81 #define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF3
82 #define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF2
87 #define CONFIG_FLASH_CFI_DRIVER
88 #define CONFIG_SYS_FLASH_BASE 0x20000000
89 #define CONFIG_SYS_FLASH_CFI
90 #define CONFIG_SYS_FLASH_CFI_AMD_RESET
91 #define CONFIG_SYS_MAX_FLASH_BANKS 1
92 #define CONFIG_SYS_MAX_FLASH_SECT 67
97 #define CONFIG_BFIN_SPI
98 #define CONFIG_ENV_SPI_MAX_HZ 30000000
100 #define CONFIG_SF_DEFAULT_SPEED 30000000
101 #define CONFIG_SPI_FLASH
102 #define CONFIG_SPI_FLASH_ALL
106 * Env Storage Settings
108 #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
109 #define CONFIG_ENV_IS_IN_SPI_FLASH
110 #define CONFIG_ENV_OFFSET 0x10000
111 #define CONFIG_ENV_SIZE 0x2000
112 #define CONFIG_ENV_SECT_SIZE 0x10000
114 #define CONFIG_ENV_IS_IN_FLASH
115 #define CONFIG_ENV_OFFSET 0x4000
116 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
117 #define CONFIG_ENV_SIZE 0x2000
118 #define CONFIG_ENV_SECT_SIZE 0x2000
120 #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
121 #define ENV_IS_EMBEDDED
123 #define CONFIG_ENV_IS_EMBEDDED_IN_LDR
125 #ifdef ENV_IS_EMBEDDED
126 /* WARNING - the following is hand-optimized to fit within
127 * the sector before the environment sector. If it throws
128 * an error during compilation remove an object here to get
129 * it linked after the configuration sector.
131 # define LDS_BOARD_TEXT \
132 arch/blackfin/lib/built-in.o (.text*); \
133 arch/blackfin/cpu/built-in.o (.text*); \
134 . = DEFINED(env_offset) ? env_offset : .; \
135 common/env_embedded.o (.text*);
142 #define CONFIG_SYS_I2C_SOFT
143 #ifdef CONFIG_SYS_I2C_SOFT
144 #define CONFIG_SYS_I2C
145 #define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF3
146 #define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF2
147 #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
148 #define CONFIG_SYS_I2C_SOFT_SPEED 50000
149 #define CONFIG_SYS_I2C_SOFT_SLAVE 0
153 * Compact Flash / IDE / ATA Settings
156 /* Enabled below option for CF support */
157 /* #define CONFIG_STAMP_CF */
158 #if defined(CONFIG_STAMP_CF)
159 #define CONFIG_MISC_INIT_R
160 #define CONFIG_DOS_PARTITION 1
161 #undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
162 #undef CONFIG_IDE_LED /* no led for ide supported */
163 #undef CONFIG_IDE_RESET /* no reset for ide supported */
165 #define CONFIG_SYS_IDE_MAXBUS 1
166 #define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS * 1)
168 #define CONFIG_SYS_ATA_BASE_ADDR 0x20200000
169 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
171 #define CONFIG_SYS_ATA_DATA_OFFSET 0x0020 /* data I/O */
172 #define CONFIG_SYS_ATA_REG_OFFSET 0x0020 /* normal register accesses */
173 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0007 /* alternate registers */
175 #define CONFIG_SYS_ATA_STRIDE 2
177 #undef CONFIG_EBIU_AMBCTL1_VAL
178 #define CONFIG_EBIU_AMBCTL1_VAL 0x99B3ffc2
185 #define CONFIG_RTC_BFIN
186 #define CONFIG_UART_CONSOLE 0
188 /* FLASH/ETHERNET uses the same async bank */
189 #define SHARED_RESOURCES 1
191 /* define to enable boot progress via leds */
192 /* #define CONFIG_SHOW_BOOT_PROGRESS */
194 /* define to enable run status via led */
195 /* #define CONFIG_STATUS_LED */
196 #ifdef CONFIG_STATUS_LED
197 #define CONFIG_GPIO_LED
198 #define CONFIG_BOARD_SPECIFIC_LED
199 /* use LED0 to indicate booting/alive */
200 #define STATUS_LED_BOOT 0
201 #define STATUS_LED_BIT GPIO_PF2
202 #define STATUS_LED_STATE STATUS_LED_ON
203 #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 4)
204 /* use LED1 to indicate crash */
205 #define STATUS_LED_CRASH 1
206 #define STATUS_LED_BIT1 GPIO_PF3
207 #define STATUS_LED_STATE1 STATUS_LED_ON
208 #define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2)
209 /* #define STATUS_LED_BIT2 GPIO_PF4 */
212 /* define to enable splash screen support */
213 /* #define CONFIG_VIDEO */
217 * Pull in common ADI header for remaining command/environment setup
219 #include <configs/bfin_adi_common.h>