2 * U-boot - Configuration file for BF533 STAMP board
5 #ifndef __CONFIG_BF533_STAMP_H__
6 #define __CONFIG_BF533_STAMP_H__
8 #include <asm/config-pre.h>
14 #define CONFIG_BFIN_CPU bf533-0.3
15 #define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
20 * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
21 * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
23 /* CONFIG_CLKIN_HZ is any value in Hz */
24 #define CONFIG_CLKIN_HZ 11059200
25 /* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
27 #define CONFIG_CLKIN_HALF 0
28 /* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
30 #define CONFIG_PLL_BYPASS 0
31 /* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
32 /* Values can range from 0-63 (where 0 means 64) */
33 #define CONFIG_VCO_MULT 45
34 /* CCLK_DIV controls the core clock divider */
35 /* Values can be 1, 2, 4, or 8 ONLY */
36 #define CONFIG_CCLK_DIV 1
37 /* SCLK_DIV controls the system clock divider */
38 /* Values can range from 1-15 */
39 #define CONFIG_SCLK_DIV 6 /* note: 1.2 boards can go faster */
45 #define CONFIG_MEM_ADD_WDTH 11
46 #define CONFIG_MEM_SIZE 128
48 #define CONFIG_EBIU_SDRRC_VAL 0x268
49 #define CONFIG_EBIU_SDGCTL_VAL 0x911109
51 #define CONFIG_EBIU_AMGCTL_VAL 0xFF
52 #define CONFIG_EBIU_AMBCTL0_VAL 0xBBC3BBC3
53 #define CONFIG_EBIU_AMBCTL1_VAL 0x99B39983
55 #define CONFIG_SYS_MONITOR_LEN (256 * 1024)
56 #define CONFIG_SYS_MALLOC_LEN (384 * 1024)
62 #define ADI_CMDS_NETWORK 1
63 #define CONFIG_NET_MULTI
64 #define CONFIG_SMC91111 1
65 #define CONFIG_SMC91111_BASE 0x20300300
66 #define SMC91111_EEPROM_INIT() \
68 bfin_write_FIO_DIR(bfin_read_FIO_DIR() | PF1 | PF0); \
69 bfin_write_FIO_FLAG_C(PF1); \
70 bfin_write_FIO_FLAG_S(PF0); \
73 #define CONFIG_HOSTNAME bf533-stamp
74 /* Uncomment next line to use fixed MAC address */
75 /* #define CONFIG_ETHADDR 02:80:ad:20:31:b8 */
81 #define CONFIG_FLASH_CFI_DRIVER
82 #define CONFIG_SYS_FLASH_BASE 0x20000000
83 #define CONFIG_SYS_FLASH_CFI
84 #define CONFIG_SYS_FLASH_CFI_AMD_RESET
85 #define CONFIG_SYS_MAX_FLASH_BANKS 1
86 #define CONFIG_SYS_MAX_FLASH_SECT 67
92 #define CONFIG_BFIN_SPI
93 #define CONFIG_ENV_SPI_MAX_HZ 30000000
94 #define CONFIG_SF_DEFAULT_SPEED 30000000
95 #define CONFIG_SPI_FLASH
96 #define CONFIG_SPI_FLASH_ATMEL
97 #define CONFIG_SPI_FLASH_SPANSION
98 #define CONFIG_SPI_FLASH_STMICRO
99 #define CONFIG_SPI_FLASH_WINBOND
103 * Env Storage Settings
105 #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
106 #define CONFIG_ENV_IS_IN_SPI_FLASH
107 #define CONFIG_ENV_OFFSET 0x10000
108 #define CONFIG_ENV_SIZE 0x2000
109 #define CONFIG_ENV_SECT_SIZE 0x10000
111 #define CONFIG_ENV_IS_IN_FLASH
112 #define CONFIG_ENV_OFFSET 0x4000
113 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
114 #define CONFIG_ENV_SIZE 0x2000
115 #define CONFIG_ENV_SECT_SIZE 0x2000
117 #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
118 #define ENV_IS_EMBEDDED
120 #define CONFIG_ENV_IS_EMBEDDED_IN_LDR
122 #ifdef ENV_IS_EMBEDDED
123 /* WARNING - the following is hand-optimized to fit within
124 * the sector before the environment sector. If it throws
125 * an error during compilation remove an object here to get
126 * it linked after the configuration sector.
128 # define LDS_BOARD_TEXT \
129 arch/blackfin/cpu/traps.o (.text .text.*); \
130 arch/blackfin/cpu/interrupt.o (.text .text.*); \
131 arch/blackfin/cpu/serial.o (.text .text.*); \
132 common/dlmalloc.o (.text .text.*); \
133 lib/crc32.o (.text .text.*); \
134 . = DEFINED(env_offset) ? env_offset : .; \
135 common/env_embedded.o (.text .text.*);
142 #define CONFIG_SOFT_I2C
143 #define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF3
144 #define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF2
148 * Compact Flash / IDE / ATA Settings
151 /* Enabled below option for CF support */
152 /* #define CONFIG_STAMP_CF */
153 #if defined(CONFIG_STAMP_CF)
154 #define CONFIG_MISC_INIT_R
155 #define CONFIG_DOS_PARTITION 1
156 #undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
157 #undef CONFIG_IDE_LED /* no led for ide supported */
158 #undef CONFIG_IDE_RESET /* no reset for ide supported */
160 #define CONFIG_SYS_IDE_MAXBUS 1
161 #define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS * 1)
163 #define CONFIG_SYS_ATA_BASE_ADDR 0x20200000
164 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
166 #define CONFIG_SYS_ATA_DATA_OFFSET 0x0020 /* data I/O */
167 #define CONFIG_SYS_ATA_REG_OFFSET 0x0020 /* normal register accesses */
168 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0007 /* alternate registers */
170 #define CONFIG_SYS_ATA_STRIDE 2
172 #undef CONFIG_EBIU_AMBCTL1_VAL
173 #define CONFIG_EBIU_AMBCTL1_VAL 0x99B3ffc2
180 #define CONFIG_RTC_BFIN
181 #define CONFIG_UART_CONSOLE 0
183 /* FLASH/ETHERNET uses the same async bank */
184 #define SHARED_RESOURCES 1
186 /* define to enable boot progress via leds */
187 /* #define CONFIG_SHOW_BOOT_PROGRESS */
189 /* define to enable run status via led */
190 /* #define CONFIG_STATUS_LED */
191 #ifdef CONFIG_STATUS_LED
192 #define CONFIG_GPIO_LED
193 #define CONFIG_BOARD_SPECIFIC_LED
194 /* use LED0 to indicate booting/alive */
195 #define STATUS_LED_BOOT 0
196 #define STATUS_LED_BIT GPIO_PF2
197 #define STATUS_LED_STATE STATUS_LED_ON
198 #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 4)
199 /* use LED1 to indicate crash */
200 #define STATUS_LED_CRASH 1
201 #define STATUS_LED_BIT1 GPIO_PF3
202 #define STATUS_LED_STATE1 STATUS_LED_ON
203 #define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2)
204 /* #define STATUS_LED_BIT2 GPIO_PF4 */
207 /* define to enable splash screen support */
208 /* #define CONFIG_VIDEO */
212 * Pull in common ADI header for remaining command/environment setup
214 #include <configs/bfin_adi_common.h>