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   1 /*
   2  * U-boot - Configuration file for BF561 EZKIT board
   3  */
   4
   5 #ifndef __CONFIG_BF561_EZKIT_H__
   6 #define __CONFIG_BF561_EZKIT_H__
   7
   8 #include <asm/blackfin-config-pre.h>
   9
  10
  11 /*
  12  * Processor Settings
  13  */
  14 #define CONFIG_BFIN_CPU             bf561-0.3
  15 #define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_BYPASS
  16
  17
  18 /*
  19  * Clock Settings
  20  *      CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
  21  *      SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
  22  */
  23 /* CONFIG_CLKIN_HZ is any value in Hz                                   */
  24 #define CONFIG_CLKIN_HZ                 30000000
  25 /* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN             */
  26 /*                                                1 = CLKIN / 2         */
  27 #define CONFIG_CLKIN_HALF               0
  28 /* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass     */
  29 /*                                                1 = bypass PLL        */
  30 #define CONFIG_PLL_BYPASS               0
  31 /* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL              */
  32 /* Values can range from 0-63 (where 0 means 64)                        */
  33 #define CONFIG_VCO_MULT                 20
  34 /* CCLK_DIV controls the core clock divider                             */
  35 /* Values can be 1, 2, 4, or 8 ONLY                                     */
  36 #define CONFIG_CCLK_DIV                 1
  37 /* SCLK_DIV controls the system clock divider                           */
  38 /* Values can range from 1-15                                           */
  39 #define CONFIG_SCLK_DIV                 6
  40
  41
  42 /*
  43  * Memory Settings
  44  */
  45 #define CONFIG_MEM_ADD_WDTH     9
  46 #define CONFIG_MEM_SIZE         64
  47
  48 #define CONFIG_EBIU_SDRRC_VAL   0x306
  49 #define CONFIG_EBIU_SDGCTL_VAL  0x91114d
  50
  51 #define CONFIG_EBIU_AMGCTL_VAL  0x3F
  52 #define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
  53 #define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
  54
  55 #define CONFIG_SYS_MONITOR_LEN  (256 * 1024)
  56 #define CONFIG_SYS_MALLOC_LEN   (128 * 1024)
  57
  58
  59 /*
  60  * Network Settings
  61  */
  62 #define ADI_CMDS_NETWORK        1
  63 #define CONFIG_DRIVER_SMC91111  1
  64 #define CONFIG_SMC91111_BASE    0x2C010300
  65 #define CONFIG_SMC_USE_32_BIT   1
  66 #define CONFIG_HOSTNAME         bf561-ezkit
  67 /* Uncomment next line to use fixed MAC address */
  68 /* #define CONFIG_ETHADDR       02:80:ad:20:31:e8 */
  69
  70
  71 /*
  72  * Flash Settings
  73  */
  74 #define CONFIG_SYS_FLASH_CFI
  75 #define CONFIG_FLASH_CFI_DRIVER
  76 #define CONFIG_SYS_FLASH_CFI_AMD_RESET
  77 #define CONFIG_SYS_FLASH_BASE           0x20000000
  78 #define CONFIG_SYS_MAX_FLASH_BANKS      1
  79 #define CONFIG_SYS_MAX_FLASH_SECT       135
  80 /* The BF561-EZKIT uses a top boot flash */
  81 #define CONFIG_ENV_IS_IN_FLASH  1
  82 #define CONFIG_ENV_ADDR         0x20004000
  83 #define CONFIG_ENV_OFFSET       (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
  84 #define CONFIG_ENV_SIZE         0x2000
  85 #define CONFIG_ENV_SECT_SIZE    0x10000
  86 #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
  87 #define ENV_IS_EMBEDDED
  88 #else
  89 #define ENV_IS_EMBEDDED_CUSTOM
  90 #endif
  91
  92
  93 /*
  94  * I2C Settings
  95  */
  96 #define CONFIG_SOFT_I2C
  97 #ifdef CONFIG_SOFT_I2C
  98 #define PF_SCL PF0
  99 #define PF_SDA PF1
 100 #define I2C_INIT \
 101         do { \
 102                 *pFIO0_DIR |= PF_SCL; \
 103                 SSYNC(); \
 104         } while (0)
 105 #define I2C_ACTIVE \
 106         do { \
 107                 *pFIO0_DIR |= PF_SDA; \
 108                 *pFIO0_INEN &= ~PF_SDA; \
 109                 SSYNC(); \
 110         } while (0)
 111 #define I2C_TRISTATE \
 112         do { \
 113                 *pFIO0_DIR &= ~PF_SDA; \
 114                 *pFIO0_INEN |= PF_SDA; \
 115                 SSYNC(); \
 116         } while (0)
 117 #define I2C_READ ((*pFIO0_FLAG_D & PF_SDA) != 0)
 118 #define I2C_SDA(bit) \
 119         do { \
 120                 if (bit) \
 121                         *pFIO0_FLAG_S = PF_SDA; \
 122                 else \
 123                         *pFIO0_FLAG_C = PF_SDA; \
 124                 SSYNC(); \
 125         } while (0)
 126 #define I2C_SCL(bit) \
 127         do { \
 128                 if (bit) \
 129                         *pFIO0_FLAG_S = PF_SCL; \
 130                 else \
 131                         *pFIO0_FLAG_C = PF_SCL; \
 132                 SSYNC(); \
 133         } while (0)
 134 #define I2C_DELAY               udelay(5)       /* 1/4 I2C clock duration */
 135
 136 #define CONFIG_SYS_I2C_SPEED            50000
 137 #define CONFIG_SYS_I2C_SLAVE            0
 138 #endif
 139
 140
 141 /*
 142  * Misc Settings
 143  */
 144 #define CONFIG_UART_CONSOLE     0
 145
 146
 147 /*
 148  * Pull in common ADI header for remaining command/environment setup
 149  */
 150 #include <configs/bfin_adi_common.h>
 151
 152 #include <asm/blackfin-config-post.h>
 153
 154 #endif                          /* __CONFIG_EZKIT561_H__ */