2 * U-boot - Configuration file for BlackStamp board
3 * Configuration by Ben Matthews for UR LLE using bf533-stamp.h
5 * See http://blackfin.uclinux.org/gf/project/blackstamp/
8 #ifndef __CONFIG_BLACKSTAMP_H__
9 #define __CONFIG_BLACKSTAMP_H__
11 #include <asm/config-pre.h>
14 * Debugging: Set these options if you're having problems
17 * #define CONFIG_DEBUG_EARLY_SERIAL
19 * #define CONFIG_DEBUG_DUMP
20 * #define CONFIG_DEBUG_DUMP_SYMS
22 #define CONFIG_PANIC_HANG 0
25 * Be sure to set the Silicon Revision Correctly
27 #define CONFIG_BFIN_CPU bf532-0.5
28 #define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER
33 #define CONFIG_SMC91111 1
34 #define CONFIG_SMC91111_BASE 0x20300300
36 /* FLASH/ETHERNET uses the same address range
37 * Depending on what you have the CPLD doing
38 * this probably isn't needed
40 #define SHARED_RESOURCES 1
42 /* Is I2C bit-banged? */
46 * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
47 * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
49 /* CONFIG_CLKIN_HZ is any value in Hz */
50 #define CONFIG_CLKIN_HZ 25000000
51 /* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
53 #define CONFIG_CLKIN_HALF 0
54 /* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
56 #define CONFIG_PLL_BYPASS 0
57 /* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
58 /* Values can range from 0-63 (where 0 means 64) */
59 #define CONFIG_VCO_MULT 16
60 /* CCLK_DIV controls the core clock divider */
61 /* Values can be 1, 2, 4, or 8 ONLY */
62 #define CONFIG_CCLK_DIV 1
63 /* SCLK_DIV controls the system clock divider */
64 /* Values can range from 1-15 */
65 #define CONFIG_SCLK_DIV 3
71 #ifdef CONFIG_SMC91111
72 #define CONFIG_IPADDR 192.168.0.15
73 #define CONFIG_NETMASK 255.255.255.0
74 #define CONFIG_GATEWAYIP 192.168.0.1
75 #define CONFIG_SERVERIP 192.168.0.2
76 #define CONFIG_HOSTNAME blackstamp
77 #define CONFIG_ROOTPATH "/checkout/uClinux-dist/romfs"
78 #define CONFIG_SYS_AUTOLOAD "no"
81 #define CONFIG_ENV_IS_IN_SPI_FLASH
82 #define CONFIG_ENV_OFFSET 0x40000
83 #define CONFIG_ENV_SIZE 0x2000
84 #define CONFIG_ENV_SECT_SIZE 0x40000
87 * SDRAM settings & memory map
90 #define CONFIG_MEM_SIZE 64 /* 128, 64, 32, 16 */
91 #define CONFIG_MEM_ADD_WDTH 10 /* 8, 9, 10, 11 */
93 #define CONFIG_SYS_MONITOR_LEN (256 << 10)
94 #define CONFIG_SYS_MALLOC_LEN (384 << 10)
100 #define CONFIG_SYS_LONGHELP 1
101 #define CONFIG_CMDLINE_EDITING 1
102 #define CONFIG_AUTO_COMPLETE 1
103 #define CONFIG_ENV_OVERWRITE 1
105 #include <config_cmd_default.h>
107 #ifdef CONFIG_SMC91111
108 # define CONFIG_CMD_DHCP
109 # define CONFIG_CMD_PING
113 #ifdef CONFIG_SYS_I2C_SOFT
114 # define CONFIG_CMD_I2C
117 #define CONFIG_CMD_BOOTLDR
118 #define CONFIG_CMD_CACHE
119 #define CONFIG_CMD_CPLBINFO
120 #define CONFIG_CMD_DATE
121 #define CONFIG_CMD_SF
122 #define CONFIG_CMD_ELF
124 #define CONFIG_BOOTDELAY 5
125 #define CONFIG_BOOTCOMMAND "run ramboot"
126 #define CONFIG_BOOTARGS \
127 "root=/dev/mtdblock0 rw " \
128 "clkin_hz=" __stringify(CONFIG_CLKIN_HZ) " " \
131 "uart" __stringify(CONFIG_UART_CONSOLE) "," \
132 __stringify(CONFIG_BAUDRATE) " " \
133 "console=ttyBF0," __stringify(CONFIG_BAUDRATE)
135 #if defined(CONFIG_CMD_NET)
136 # if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
137 # define UBOOT_ENV_FILE "u-boot.bin"
139 # define UBOOT_ENV_FILE "u-boot.ldr"
141 # if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
143 # define UBOOT_ENV_UPDATE \
144 "eeprom write $(loadaddr) 0x0 $(filesize)"
146 # define UBOOT_ENV_UPDATE \
147 "sf probe " __stringify(BFIN_BOOT_SPI_SSEL) ";" \
148 "sf erase 0 0x40000;" \
149 "sf write $(loadaddr) 0 $(filesize)"
152 # define UBOOT_ENV_UPDATE \
153 "protect off 0x20000000 0x2003FFFF;" \
154 "erase 0x20000000 0x2003FFFF;" \
155 "cp.b $(loadaddr) 0x20000000 $(filesize)"
157 # define NETWORK_ENV_SETTINGS \
158 "ubootfile=" UBOOT_ENV_FILE "\0" \
160 "tftp $(loadaddr) $(ubootfile);" \
163 "addip=set bootargs $(bootargs) " \
164 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):" \
165 "$(hostname):eth0:off" \
167 "ramargs=set bootargs " CONFIG_BOOTARGS "\0" \
169 "tftp $(loadaddr) uImage;" \
174 "nfsargs=set bootargs " \
175 "root=/dev/nfs rw " \
176 "nfsroot=$(serverip):$(rootpath),tcp,nfsvers=3" \
179 "tftp $(loadaddr) vmImage;" \
185 # define NETWORK_ENV_SETTINGS
191 #define CONFIG_BAUDRATE 57600
192 #define CONFIG_LOADS_ECHO 1
193 #define CONFIG_UART_CONSOLE 0
194 #define CONFIG_BFIN_SERIAL
198 * By default PF2 is used as SDA and PF3 as SCL on the Stamp board
199 * Located on the expansion connector on pins 86/85
200 * Note these pins are arbitrarily chosen because we aren't using
201 * them yet. You can (and probably should) change these values!
203 #ifdef CONFIG_SYS_I2C_SOFT
204 #define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF9
205 #define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF8
206 #define CONFIG_SYS_I2C_SOFT_SPEED 50000
207 #define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
211 * Miscellaneous configurable options
213 #define CONFIG_RTC_BFIN 1
216 * Serial Flash Infomation
218 #define CONFIG_BFIN_SPI
219 /* For the M25P64 SCK Should be Kept < 15Mhz */
220 #define CONFIG_ENV_SPI_MAX_HZ 15000000
221 #define CONFIG_SF_DEFAULT_SPEED 15000000
222 #define CONFIG_SPI_FLASH
223 #define CONFIG_SPI_FLASH_STMICRO
226 * FLASH organization and environment definitions
229 #define CONFIG_EBIU_AMGCTL_VAL 0xFF
230 #define CONFIG_EBIU_AMBCTL0_VAL 0xBBC3BBC3
231 #define CONFIG_EBIU_AMBCTL1_VAL 0x99B39983
232 #define CONFIG_EBIU_SDRRC_VAL 0x268
233 #define CONFIG_EBIU_SDGCTL_VAL 0x911109
235 /* Even though Rev C boards have Parallel Flash
236 * We aren't supporting it. Newer versions of the
237 * hardware don't support Parallel Flash at all.
239 #define CONFIG_SYS_NO_FLASH
240 #undef CONFIG_CMD_IMLS
241 #undef CONFIG_CMD_JFFS2
242 #undef CONFIG_CMD_FLASH