2 * bluestone.h - configuration for Bluestone (APM821XX)
4 * Copyright (c) 2010, Applied Micro Circuits Corporation
5 * Author: Tirumala R Marri <tmarri@apm.com>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * High Level Configuration Options
29 #define CONFIG_APM821XX 1 /* APM821XX series */
30 #define CONFIG_HOSTNAME bluestone
32 #define CONFIG_4xx 1 /* ... PPC4xx family */
35 #ifndef CONFIG_SYS_TEXT_BASE
36 #define CONFIG_SYS_TEXT_BASE 0xFFFA0000
40 * Include common defines/options for all AMCC eval boards
42 #include "amcc-common.h"
43 #define CONFIG_SYS_CLK_FREQ 50000000
45 #define CONFIG_BOARD_TYPES 1 /* support board types */
46 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
47 #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
50 * Base addresses -- Note these are effective addresses where the
51 * actual resources get mapped (not physical addresses)
54 /* later mapped to this addr */
55 #define CONFIG_SYS_FLASH_BASE 0xFFF00000
56 #define CONFIG_SYS_FLASH_SIZE (4 << 20) /* 1MB usable */
58 /* EBC Boot Space: 0xFF000000 */
59 #define CONFIG_SYS_BOOT_BASE_ADDR 0xFF000000
60 #define CONFIG_SYS_OCM_BASE 0xE3000000 /* OCM: 32k */
61 #define CONFIG_SYS_SRAM_BASE 0xE8000000 /* SRAM: 256k */
62 #define CONFIG_SYS_AHB_BASE 0xE2000000 /* internal AHB peripherals*/
64 #define CONFIG_SYS_SRAM_SIZE (256 << 10)
66 * Initial RAM & stack pointer (placed in OCM)
68 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */
69 #define CONFIG_SYS_INIT_RAM_END (4 << 10)
70 #define CONFIG_SYS_GBL_DATA_SIZE 256 /* num bytes initial data */
71 #define CONFIG_SYS_GBL_DATA_OFFSET \
72 (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
73 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
79 * Define here the location of the environment variables (FLASH).
81 #define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
86 #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
87 #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
88 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
89 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
90 /* max number of memory banks */
91 #define CONFIG_SYS_MAX_FLASH_BANKS 1
92 /* max number of sectors on one chip */
93 #define CONFIG_SYS_MAX_FLASH_SECT 80
94 /* Timeout for Flash Erase (in ms) */
95 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000
96 /* Timeout for Flash Write (in ms) */
97 #define CONFIG_SYS_FLASH_WRITE_TOUT 500
98 /* use buffered writes (20x faster) */
99 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
100 /* print 'E' for empty sector on flinfo */
101 #define CONFIG_SYS_FLASH_EMPTY_INFO
102 #ifdef CONFIG_ENV_IS_IN_FLASH
103 #define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
104 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
105 #define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
106 /* Address and size of Redundant Environment Sector */
107 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
108 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
109 #endif /* CONFIG_ENV_IS_IN_FLASH */
112 #define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */
113 #define SPD_EEPROM_ADDRESS {0x53, 0x51} /* SPD i2c spd addresses */
114 #define CONFIG_PPC4xx_DDR_AUTOCALIBRATION /* IBM DDR autocalibration */
115 #define CONFIG_AUTOCALIB "silent\0" /* default is non-verbose */
116 #define CONFIG_DDR_ECC 1 /* with ECC support */
121 #define CONFIG_CONS_INDEX 1 /* Use UART0 */
126 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed */
127 #define CONFIG_SYS_I2C_MULTI_EEPROMS
128 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
129 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
130 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
131 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 /* Data sheet */
133 /* I2C bootstrap EEPROM */
134 #define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x52
135 #define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0
136 #define CONFIG_4xx_CONFIG_BLOCKSIZE 16
141 #define CONFIG_IBM_EMAC4_V4 1
142 #define CONFIG_EMAC_PHY_MODE EMAC_PHY_MODE_NONE_RGMII
143 #define CONFIG_HAS_ETH0
144 /* PHY address, See schematics */
145 #define CONFIG_PHY_ADDR 0x1f
146 /* reset phy upon startup */
147 #define CONFIG_PHY_RESET 1
148 /* Include GbE speed/duplex detection */
149 #define CONFIG_PHY_GIGE 1
150 #define CONFIG_PHY_DYNAMIC_ANEG 1
153 * External Bus Controller (EBC) Setup
155 #define CONFIG_SYS_EBC_CFG (EBC_CFG_LE_LOCK | \
156 EBC_CFG_PTD_ENABLE | \
157 EBC_CFG_RTC_2048PERCLK | \
161 EBC_CFG_OEO_PREVIOUS)
163 #define CONFIG_SYS_EBC_PB0AP (EBC_BXAP_BME_DISABLED | \
164 EBC_BXAP_TWT_ENCODE(64) | \
165 EBC_BXAP_BCE_DISABLE | \
166 EBC_BXAP_BCT_2TRANS | \
167 EBC_BXAP_CSN_ENCODE(1) | \
168 EBC_BXAP_OEN_ENCODE(2) | \
169 EBC_BXAP_WBN_ENCODE(2) | \
170 EBC_BXAP_WBF_ENCODE(2) | \
171 EBC_BXAP_TH_ENCODE(7) | \
172 EBC_BXAP_SOR_DELAYED | \
173 EBC_BXAP_BEM_WRITEONLY | \
174 EBC_BXAP_PEN_DISABLED)
175 /* Peripheral Bank Configuration Register - EBC_BxCR */
176 #define CONFIG_SYS_EBC_PB0CR \
177 (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | \
183 #endif /* __CONFIG_H */