2 * (C) Copyright 2011 CompuLab, Ltd.
3 * Mike Rapoport <mike@compulab.co.il>
4 * Igor Grinberg <grinberg@compulab.co.il>
6 * Based on omap3_beagle.h
7 * (C) Copyright 2006-2008
9 * Richard Woodruff <r-woodruff2@ti.com>
10 * Syed Mohammed Khasim <x0khasim@ti.com>
12 * Configuration settings for the CompuLab CM-T35 and CM-T3730 boards
14 * SPDX-License-Identifier: GPL-2.0+
20 #define CONFIG_SYS_CACHELINE_SIZE 64
23 * High Level Configuration Options
25 #define CONFIG_OMAP /* in a TI OMAP core */
26 #define CONFIG_OMAP_GPIO
27 #define CONFIG_CM_T3X /* working with CM-T35 and CM-T3730 */
28 #define CONFIG_OMAP_COMMON
29 /* Common ARM Erratas */
30 #define CONFIG_ARM_ERRATA_454179
31 #define CONFIG_ARM_ERRATA_430973
32 #define CONFIG_ARM_ERRATA_621766
34 #define CONFIG_SDRC /* The chip has SDRC controller */
36 #include <asm/arch/cpu.h> /* get chip and board defs */
37 #include <asm/arch/omap.h>
40 * Display CPU and Board information
42 #define CONFIG_DISPLAY_CPUINFO
43 #define CONFIG_DISPLAY_BOARDINFO
46 #define V_OSCK 26000000 /* Clock output from T2 */
47 #define V_SCLK (V_OSCK >> 1)
49 #define CONFIG_MISC_INIT_R
51 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
52 #define CONFIG_SETUP_MEMORY_TAGS
53 #define CONFIG_INITRD_TAG
54 #define CONFIG_REVISION_TAG
55 #define CONFIG_SERIAL_TAG
58 * Size of malloc() pool
60 #define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */
62 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
69 * NS16550 Configuration
71 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
73 #define CONFIG_SYS_NS16550_SERIAL
74 #define CONFIG_SYS_NS16550_REG_SIZE (-4)
75 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
78 * select serial console configuration
80 #define CONFIG_CONS_INDEX 3
81 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
82 #define CONFIG_SERIAL3 3 /* UART3 */
84 /* allow to overwrite serial and ethaddr */
85 #define CONFIG_ENV_OVERWRITE
86 #define CONFIG_BAUDRATE 115200
87 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
90 #define CONFIG_GENERIC_MMC
92 #define CONFIG_OMAP_HSMMC
93 #define CONFIG_DOS_PARTITION
96 #define CONFIG_USB_OMAP3
97 #define CONFIG_USB_EHCI
98 #define CONFIG_USB_EHCI_OMAP
99 #define CONFIG_USB_STORAGE
100 #define CONFIG_USB_MUSB_UDC
101 #define CONFIG_TWL4030_USB
103 /* USB device configuration */
104 #define CONFIG_USB_DEVICE
105 #define CONFIG_USB_TTY
106 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
108 /* commands to include */
109 #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
110 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
111 #define CONFIG_MTD_PARTITIONS
112 #define MTDIDS_DEFAULT "nand0=nand"
113 #define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\
114 "1920k(u-boot),256k(u-boot-env),"\
117 #define CONFIG_CMD_NAND /* NAND support */
119 #define CONFIG_SYS_NO_FLASH
120 #define CONFIG_SYS_I2C
121 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000
122 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1
123 #define CONFIG_SYS_I2C_OMAP34XX
124 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
125 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
126 #define CONFIG_SYS_I2C_EEPROM_BUS 0
127 #define CONFIG_I2C_MULTI_BUS
132 #define CONFIG_TWL4030_POWER
133 #define CONFIG_TWL4030_LED
138 #define CONFIG_NAND_OMAP_GPMC
139 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
141 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
142 /* to access nand at */
144 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
147 /* Environment information */
148 #define CONFIG_EXTRA_ENV_SETTINGS \
149 "loadaddr=0x82000000\0" \
151 "console=ttyO2,115200n8\0" \
154 "dvimode=1024x768MR-16@60\0" \
155 "defaultdisplay=dvi\0" \
157 "mmcroot=/dev/mmcblk0p2 rw\0" \
158 "mmcrootfstype=ext4 rootwait\0" \
159 "nandroot=/dev/mtdblock4 rw\0" \
160 "nandrootfstype=ubifs\0" \
161 "mmcargs=setenv bootargs console=${console} " \
162 "mpurate=${mpurate} " \
164 "omapfb.mode=dvi:${dvimode} " \
165 "omapdss.def_disp=${defaultdisplay} " \
167 "rootfstype=${mmcrootfstype}\0" \
168 "nandargs=setenv bootargs console=${console} " \
169 "mpurate=${mpurate} " \
171 "omapfb.mode=dvi:${dvimode} " \
172 "omapdss.def_disp=${defaultdisplay} " \
173 "root=${nandroot} " \
174 "rootfstype=${nandrootfstype}\0" \
175 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
176 "bootscript=echo Running bootscript from mmc ...; " \
177 "source ${loadaddr}\0" \
178 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
179 "mmcboot=echo Booting from mmc ...; " \
181 "bootm ${loadaddr}\0" \
182 "nandboot=echo Booting from nand ...; " \
184 "nand read ${loadaddr} 2a0000 400000; " \
185 "bootm ${loadaddr}\0" \
187 #define CONFIG_BOOTCOMMAND \
188 "mmc dev ${mmcdev}; if mmc rescan; then " \
189 "if run loadbootscript; then " \
192 "if run loaduimage; then " \
194 "else run nandboot; " \
197 "else run nandboot; fi"
200 * Miscellaneous configurable options
202 #define CONFIG_AUTO_COMPLETE
203 #define CONFIG_CMDLINE_EDITING
204 #define CONFIG_TIMESTAMP
205 #define CONFIG_SYS_AUTOLOAD "no"
206 #define CONFIG_SYS_LONGHELP /* undef to save memory */
207 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
208 /* Print Buffer Size */
209 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
210 sizeof(CONFIG_SYS_PROMPT) + 16)
211 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
212 /* Boot Argument Buffer Size */
213 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
215 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */
217 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
218 0x01F00000) /* 31MB */
220 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */
224 * OMAP3 has 12 GP timers, they can be driven by the system clock
225 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
226 * This rate is divided by a local divisor.
228 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
229 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
231 /*-----------------------------------------------------------------------
232 * Physical Memory Map
234 #define CONFIG_NR_DRAM_BANKS 1 /* CS1 is never populated */
235 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
237 /*-----------------------------------------------------------------------
238 * FLASH and environment organization
241 /* **** PISMO SUPPORT *** */
242 /* Monitor at start of flash */
243 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
244 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
246 #define CONFIG_ENV_IS_IN_NAND
247 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
248 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
249 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
251 #if defined(CONFIG_CMD_NET)
252 #define CONFIG_SMC911X
253 #define CONFIG_SMC911X_32_BIT
254 #define CM_T3X_SMC911X_BASE 0x2C000000
255 #define SB_T35_SMC911X_BASE (CM_T3X_SMC911X_BASE + (16 << 20))
256 #define CONFIG_SMC911X_BASE CM_T3X_SMC911X_BASE
257 #endif /* (CONFIG_CMD_NET) */
259 /* additions for new relocation code, must be added to all boards */
260 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
261 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
262 #define CONFIG_SYS_INIT_RAM_SIZE 0x800
263 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
264 CONFIG_SYS_INIT_RAM_SIZE - \
265 GENERATED_GBL_DATA_SIZE)
268 #define CONFIG_STATUS_LED /* Status LED enabled */
269 #define CONFIG_BOARD_SPECIFIC_LED
270 #define CONFIG_GPIO_LED
271 #define GREEN_LED_GPIO 186 /* CM-T35 Green LED is GPIO186 */
272 #define GREEN_LED_DEV 0
273 #define STATUS_LED_BIT GREEN_LED_GPIO
274 #define STATUS_LED_STATE STATUS_LED_ON
275 #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
276 #define STATUS_LED_BOOT GREEN_LED_DEV
278 #define CONFIG_SPLASHIMAGE_GUARD
281 #ifdef CONFIG_STATUS_LED
282 #define CONFIG_OMAP3_GPIO_6 /* GPIO186 is in GPIO bank 6 */
285 /* Display Configuration */
286 #define CONFIG_OMAP3_GPIO_2
287 #define CONFIG_OMAP3_GPIO_5
288 #define CONFIG_VIDEO_OMAP3
289 #define LCD_BPP LCD_COLOR16
292 #define CONFIG_SPLASH_SCREEN
293 #define CONFIG_SPLASH_SOURCE
294 #define CONFIG_CMD_BMP
295 #define CONFIG_BMP_16BPP
296 #define CONFIG_SCF0403_LCD
298 #define CONFIG_OMAP3_SPI
300 /* Defines for SPL */
301 #define CONFIG_SPL_FRAMEWORK
302 #define CONFIG_SPL_NAND_SIMPLE
304 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
305 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
306 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
307 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
309 #define CONFIG_SPL_BOARD_INIT
310 #define CONFIG_SPL_LIBCOMMON_SUPPORT
311 #define CONFIG_SPL_LIBDISK_SUPPORT
312 #define CONFIG_SPL_I2C_SUPPORT
313 #define CONFIG_SPL_LIBGENERIC_SUPPORT
314 #define CONFIG_SPL_MMC_SUPPORT
315 #define CONFIG_SPL_FAT_SUPPORT
316 #define CONFIG_SPL_SERIAL_SUPPORT
317 #define CONFIG_SPL_NAND_SUPPORT
318 #define CONFIG_SPL_NAND_BASE
319 #define CONFIG_SPL_NAND_DRIVERS
320 #define CONFIG_SPL_NAND_ECC
321 #define CONFIG_SPL_GPIO_SUPPORT
322 #define CONFIG_SPL_POWER_SUPPORT
323 #define CONFIG_SPL_OMAP3_ID_NAND
324 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
326 /* NAND boot config */
327 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
328 #define CONFIG_SYS_NAND_PAGE_COUNT 64
329 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
330 #define CONFIG_SYS_NAND_OOBSIZE 64
331 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
332 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
334 * Use the ECC/OOB layout from omap_gpmc.h that matches your chip:
335 * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT
337 #define CONFIG_SYS_NAND_ECCPOS { 1, 2, 3, 4, 5, 6, 7, 8, 9, \
339 #define CONFIG_SYS_NAND_ECCSIZE 512
340 #define CONFIG_SYS_NAND_ECCBYTES 3
341 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
343 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
344 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
346 #define CONFIG_SPL_TEXT_BASE 0x40200800
347 #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */
350 * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the
351 * older x-loader implementations. And move the BSS area so that it
352 * doesn't overlap with TEXT_BASE.
354 #define CONFIG_SYS_TEXT_BASE 0x80008000
355 #define CONFIG_SPL_BSS_START_ADDR 0x80100000
356 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
358 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000
359 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
362 #define CONFIG_CMD_EEPROM
363 #define CONFIG_ENV_EEPROM_IS_ON_I2C
364 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
365 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
366 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
367 #define CONFIG_SYS_EEPROM_SIZE 256
369 #define CONFIG_CMD_EEPROM_LAYOUT
370 #define CONFIG_EEPROM_LAYOUT_HELP_STRING "legacy, v1, v2, v3"
372 #endif /* __CONFIG_H */