2 * (C) Copyright 2011 CompuLab, Ltd.
3 * Mike Rapoport <mike@compulab.co.il>
4 * Igor Grinberg <grinberg@compulab.co.il>
6 * Based on omap3_beagle.h
7 * (C) Copyright 2006-2008
9 * Richard Woodruff <r-woodruff2@ti.com>
10 * Syed Mohammed Khasim <x0khasim@ti.com>
12 * Configuration settings for the CompuLab CM-T35 and CM-T3730 boards
14 * SPDX-License-Identifier: GPL-2.0+
20 #define CONFIG_SYS_CACHELINE_SIZE 64
23 * High Level Configuration Options
25 #define CONFIG_CM_T3X /* working with CM-T35 and CM-T3730 */
27 #include <asm/arch/cpu.h> /* get chip and board defs */
28 #include <asm/arch/omap.h>
31 #define V_OSCK 26000000 /* Clock output from T2 */
32 #define V_SCLK (V_OSCK >> 1)
34 #define CONFIG_MISC_INIT_R
36 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
37 #define CONFIG_SETUP_MEMORY_TAGS
38 #define CONFIG_INITRD_TAG
39 #define CONFIG_REVISION_TAG
40 #define CONFIG_SERIAL_TAG
43 * Size of malloc() pool
45 #define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */
47 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
54 * NS16550 Configuration
56 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
58 #define CONFIG_SYS_NS16550_SERIAL
59 #define CONFIG_SYS_NS16550_REG_SIZE (-4)
60 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
63 * select serial console configuration
65 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
66 #define CONFIG_SERIAL3 3 /* UART3 */
68 /* allow to overwrite serial and ethaddr */
69 #define CONFIG_ENV_OVERWRITE
70 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
73 /* USB device configuration */
74 #define CONFIG_USB_DEVICE
75 #define CONFIG_USB_TTY
77 /* commands to include */
78 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
79 #define CONFIG_MTD_PARTITIONS
81 #define CONFIG_SYS_I2C
82 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
83 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
84 #define CONFIG_SYS_I2C_EEPROM_BUS 0
85 #define CONFIG_I2C_MULTI_BUS
90 #define CONFIG_TWL4030_LED
95 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
97 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
98 /* to access nand at */
100 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
103 /* Environment information */
104 #define CONFIG_EXTRA_ENV_SETTINGS \
105 "loadaddr=0x82000000\0" \
107 "console=ttyO2,115200n8\0" \
110 "dvimode=1024x768MR-16@60\0" \
111 "defaultdisplay=dvi\0" \
113 "mmcroot=/dev/mmcblk0p2 rw\0" \
114 "mmcrootfstype=ext4 rootwait\0" \
115 "nandroot=/dev/mtdblock4 rw\0" \
116 "nandrootfstype=ubifs\0" \
117 "mmcargs=setenv bootargs console=${console} " \
118 "mpurate=${mpurate} " \
120 "omapfb.mode=dvi:${dvimode} " \
121 "omapdss.def_disp=${defaultdisplay} " \
123 "rootfstype=${mmcrootfstype}\0" \
124 "nandargs=setenv bootargs console=${console} " \
125 "mpurate=${mpurate} " \
127 "omapfb.mode=dvi:${dvimode} " \
128 "omapdss.def_disp=${defaultdisplay} " \
129 "root=${nandroot} " \
130 "rootfstype=${nandrootfstype}\0" \
131 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
132 "bootscript=echo Running bootscript from mmc ...; " \
133 "source ${loadaddr}\0" \
134 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
135 "mmcboot=echo Booting from mmc ...; " \
137 "bootm ${loadaddr}\0" \
138 "nandboot=echo Booting from nand ...; " \
140 "nand read ${loadaddr} 2a0000 400000; " \
141 "bootm ${loadaddr}\0" \
143 #define CONFIG_BOOTCOMMAND \
144 "mmc dev ${mmcdev}; if mmc rescan; then " \
145 "if run loadbootscript; then " \
148 "if run loaduimage; then " \
150 "else run nandboot; " \
153 "else run nandboot; fi"
156 * Miscellaneous configurable options
158 #define CONFIG_TIMESTAMP
159 #define CONFIG_SYS_AUTOLOAD "no"
161 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */
163 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
164 0x01F00000) /* 31MB */
166 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */
170 * OMAP3 has 12 GP timers, they can be driven by the system clock
171 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
172 * This rate is divided by a local divisor.
174 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
175 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
177 /*-----------------------------------------------------------------------
178 * Physical Memory Map
180 #define CONFIG_NR_DRAM_BANKS 1 /* CS1 is never populated */
181 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
183 /*-----------------------------------------------------------------------
184 * FLASH and environment organization
187 /* **** PISMO SUPPORT *** */
188 /* Monitor at start of flash */
189 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
190 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
192 #define CONFIG_ENV_OFFSET 0x260000
193 #define CONFIG_ENV_ADDR 0x260000
195 /* additions for new relocation code, must be added to all boards */
196 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
197 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
198 #define CONFIG_SYS_INIT_RAM_SIZE 0x800
199 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
200 CONFIG_SYS_INIT_RAM_SIZE - \
201 GENERATED_GBL_DATA_SIZE)
204 #define GREEN_LED_GPIO 186 /* CM-T35 Green LED is GPIO186 */
206 #define CONFIG_SPLASHIMAGE_GUARD
208 /* Display Configuration */
209 #define CONFIG_VIDEO_OMAP3
210 #define LCD_BPP LCD_COLOR16
212 #define CONFIG_SPLASH_SCREEN
213 #define CONFIG_SPLASH_SOURCE
214 #define CONFIG_BMP_16BPP
215 #define CONFIG_SCF0403_LCD
217 /* Defines for SPL */
219 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
220 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
222 #define CONFIG_SPL_NAND_BASE
223 #define CONFIG_SPL_NAND_DRIVERS
224 #define CONFIG_SPL_NAND_ECC
226 /* NAND boot config */
227 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
228 #define CONFIG_SYS_NAND_PAGE_COUNT 64
229 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
230 #define CONFIG_SYS_NAND_OOBSIZE 64
231 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
232 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
234 * Use the ECC/OOB layout from omap_gpmc.h that matches your chip:
235 * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT
237 #define CONFIG_SYS_NAND_ECCPOS { 1, 2, 3, 4, 5, 6, 7, 8, 9, \
239 #define CONFIG_SYS_NAND_ECCSIZE 512
240 #define CONFIG_SYS_NAND_ECCBYTES 3
241 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
243 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
244 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
246 #define CONFIG_SPL_TEXT_BASE 0x40200800
247 #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
248 CONFIG_SPL_TEXT_BASE)
251 * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the
252 * older x-loader implementations. And move the BSS area so that it
253 * doesn't overlap with TEXT_BASE.
255 #define CONFIG_SPL_BSS_START_ADDR 0x80100000
256 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
258 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000
259 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
262 #define CONFIG_ENV_EEPROM_IS_ON_I2C
263 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
264 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
265 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
266 #define CONFIG_SYS_EEPROM_SIZE 256
268 #endif /* __CONFIG_H */