2 * (C) Copyright 2011 CompuLab, Ltd.
3 * Mike Rapoport <mike@compulab.co.il>
4 * Igor Grinberg <grinberg@compulab.co.il>
6 * Based on omap3_beagle.h
7 * (C) Copyright 2006-2008
9 * Richard Woodruff <r-woodruff2@ti.com>
10 * Syed Mohammed Khasim <x0khasim@ti.com>
12 * Configuration settings for the CompuLab CM-T35 and CM-T3730 boards
14 * SPDX-License-Identifier: GPL-2.0+
21 * High Level Configuration Options
23 #define CONFIG_OMAP /* in a TI OMAP core */
24 #define CONFIG_OMAP34XX /* which is a 34XX */
25 #define CONFIG_OMAP_GPIO
26 #define CONFIG_CMD_GPIO
27 #define CONFIG_CM_T3X /* working with CM-T35 and CM-T3730 */
28 #define CONFIG_OMAP_COMMON
30 #define CONFIG_SYS_TEXT_BASE 0x80008000
32 #define CONFIG_SDRC /* The chip has SDRC controller */
34 #include <asm/arch/cpu.h> /* get chip and board defs */
35 #include <asm/arch/omap3.h>
38 * Display CPU and Board information
40 #define CONFIG_DISPLAY_CPUINFO
41 #define CONFIG_DISPLAY_BOARDINFO
44 #define V_OSCK 26000000 /* Clock output from T2 */
45 #define V_SCLK (V_OSCK >> 1)
47 #define CONFIG_MISC_INIT_R
49 #define CONFIG_OF_LIBFDT 1
51 * The early kernel mapping on ARM currently only maps from the base of DRAM
52 * to the end of the kernel image. The kernel is loaded at DRAM base + 0x8000.
53 * The early kernel pagetable uses DRAM base + 0x4000 to DRAM base + 0x8000,
54 * so that leaves DRAM base to DRAM base + 0x4000 available.
56 #define CONFIG_SYS_BOOTMAPSZ 0x4000
58 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
59 #define CONFIG_SETUP_MEMORY_TAGS
60 #define CONFIG_INITRD_TAG
61 #define CONFIG_REVISION_TAG
62 #define CONFIG_SERIAL_TAG
65 * Size of malloc() pool
67 #define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */
69 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
76 * NS16550 Configuration
78 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
80 #define CONFIG_SYS_NS16550
81 #define CONFIG_SYS_NS16550_SERIAL
82 #define CONFIG_SYS_NS16550_REG_SIZE (-4)
83 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
86 * select serial console configuration
88 #define CONFIG_CONS_INDEX 3
89 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
90 #define CONFIG_SERIAL3 3 /* UART3 */
92 /* allow to overwrite serial and ethaddr */
93 #define CONFIG_ENV_OVERWRITE
94 #define CONFIG_BAUDRATE 115200
95 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
98 #define CONFIG_GENERIC_MMC
100 #define CONFIG_OMAP_HSMMC
101 #define CONFIG_DOS_PARTITION
104 #define CONFIG_USB_OMAP3
105 #define CONFIG_USB_EHCI
106 #define CONFIG_USB_EHCI_OMAP
107 #define CONFIG_USB_ULPI
108 #define CONFIG_USB_ULPI_VIEWPORT_OMAP
109 #define CONFIG_USB_STORAGE
110 #define CONFIG_MUSB_UDC
111 #define CONFIG_TWL4030_USB
112 #define CONFIG_CMD_USB
114 /* USB device configuration */
115 #define CONFIG_USB_DEVICE
116 #define CONFIG_USB_TTY
117 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
119 /* commands to include */
120 #include <config_cmd_default.h>
122 #define CONFIG_CMD_CACHE
123 #define CONFIG_CMD_EXT2 /* EXT2 Support */
124 #define CONFIG_CMD_FAT /* FAT support */
125 #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
126 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
127 #define CONFIG_MTD_PARTITIONS
128 #define MTDIDS_DEFAULT "nand0=nand"
129 #define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\
130 "1920k(u-boot),256k(u-boot-env),"\
133 #define CONFIG_CMD_I2C /* I2C serial bus support */
134 #define CONFIG_CMD_MMC /* MMC support */
135 #define CONFIG_CMD_NAND /* NAND support */
136 #define CONFIG_CMD_DHCP
137 #define CONFIG_CMD_PING
139 #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
140 #undef CONFIG_CMD_FPGA /* FPGA configuration Support */
141 #undef CONFIG_CMD_IMLS /* List all found images */
143 #define CONFIG_SYS_NO_FLASH
144 #define CONFIG_HARD_I2C
145 #define CONFIG_SYS_I2C_SPEED 100000
146 #define CONFIG_SYS_I2C_SLAVE 1
147 #define CONFIG_DRIVER_OMAP34XX_I2C
148 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
149 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
150 #define CONFIG_I2C_MULTI_BUS
155 #define CONFIG_TWL4030_POWER
156 #define CONFIG_TWL4030_LED
161 #define CONFIG_SYS_NAND_QUIET_TEST
162 #define CONFIG_NAND_OMAP_GPMC
163 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
165 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
166 /* to access nand at */
168 #define GPMC_NAND_ECC_LP_x8_LAYOUT
170 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
172 /* Environment information */
173 #define CONFIG_BOOTDELAY 3
174 #define CONFIG_ZERO_BOOTDELAY_CHECK
176 #define CONFIG_EXTRA_ENV_SETTINGS \
177 "loadaddr=0x82000000\0" \
179 "console=ttyS2,115200n8\0" \
182 "dvimode=1024x768MR-16@60\0" \
183 "defaultdisplay=dvi\0" \
185 "mmcroot=/dev/mmcblk0p2 rw\0" \
186 "mmcrootfstype=ext4 rootwait\0" \
187 "nandroot=/dev/mtdblock4 rw\0" \
188 "nandrootfstype=ubifs\0" \
189 "mmcargs=setenv bootargs console=${console} " \
190 "mpurate=${mpurate} " \
192 "omapfb.mode=dvi:${dvimode} " \
194 "omapdss.def_disp=${defaultdisplay} " \
196 "rootfstype=${mmcrootfstype}\0" \
197 "nandargs=setenv bootargs console=${console} " \
198 "mpurate=${mpurate} " \
200 "omapfb.mode=dvi:${dvimode} " \
202 "omapdss.def_disp=${defaultdisplay} " \
203 "root=${nandroot} " \
204 "rootfstype=${nandrootfstype}\0" \
205 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
206 "bootscript=echo Running bootscript from mmc ...; " \
207 "source ${loadaddr}\0" \
208 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
209 "mmcboot=echo Booting from mmc ...; " \
211 "bootm ${loadaddr}\0" \
212 "nandboot=echo Booting from nand ...; " \
214 "nand read ${loadaddr} 2a0000 400000; " \
215 "bootm ${loadaddr}\0" \
217 #define CONFIG_BOOTCOMMAND \
218 "mmc dev ${mmcdev}; if mmc rescan; then " \
219 "if run loadbootscript; then " \
222 "if run loaduimage; then " \
224 "else run nandboot; " \
227 "else run nandboot; fi"
230 * Miscellaneous configurable options
232 #define CONFIG_AUTO_COMPLETE
233 #define CONFIG_CMDLINE_EDITING
234 #define CONFIG_TIMESTAMP
235 #define CONFIG_SYS_AUTOLOAD "no"
236 #define CONFIG_SYS_LONGHELP /* undef to save memory */
237 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
238 #define CONFIG_SYS_PROMPT "CM-T3x # "
239 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
240 /* Print Buffer Size */
241 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
242 sizeof(CONFIG_SYS_PROMPT) + 16)
243 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
244 /* Boot Argument Buffer Size */
245 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
247 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */
249 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
250 0x01F00000) /* 31MB */
252 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */
256 * OMAP3 has 12 GP timers, they can be driven by the system clock
257 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
258 * This rate is divided by a local divisor.
260 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
261 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
262 #define CONFIG_SYS_HZ 1000
264 /*-----------------------------------------------------------------------
265 * Physical Memory Map
267 #define CONFIG_NR_DRAM_BANKS 1 /* CS1 is never populated */
268 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
270 /*-----------------------------------------------------------------------
271 * FLASH and environment organization
274 /* **** PISMO SUPPORT *** */
275 /* Configure the PISMO */
276 #define PISMO1_NAND_SIZE GPMC_SIZE_128M
278 /* Monitor at start of flash */
279 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
280 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
282 #define CONFIG_ENV_IS_IN_NAND
283 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
284 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
285 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
287 #if defined(CONFIG_CMD_NET)
288 #define CONFIG_SMC911X
289 #define CONFIG_SMC911X_32_BIT
290 #define CM_T3X_SMC911X_BASE 0x2C000000
291 #define SB_T35_SMC911X_BASE (CM_T3X_SMC911X_BASE + (16 << 20))
292 #define CONFIG_SMC911X_BASE CM_T3X_SMC911X_BASE
293 #endif /* (CONFIG_CMD_NET) */
295 /* additions for new relocation code, must be added to all boards */
296 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
297 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
298 #define CONFIG_SYS_INIT_RAM_SIZE 0x800
299 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
300 CONFIG_SYS_INIT_RAM_SIZE - \
301 GENERATED_GBL_DATA_SIZE)
304 #define CONFIG_STATUS_LED /* Status LED enabled */
305 #define CONFIG_BOARD_SPECIFIC_LED
306 #define STATUS_LED_GREEN 0
307 #define STATUS_LED_BIT STATUS_LED_GREEN
308 #define STATUS_LED_STATE STATUS_LED_ON
309 #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
310 #define STATUS_LED_BOOT STATUS_LED_BIT
311 #define GREEN_LED_GPIO 186 /* CM-T35 Green LED is GPIO186 */
313 #define CONFIG_SPLASHIMAGE_GUARD
316 #ifdef CONFIG_STATUS_LED
317 #define CONFIG_OMAP3_GPIO_6 /* GPIO186 is in GPIO bank 6 */
320 /* Display Configuration */
321 #define CONFIG_OMAP3_GPIO_2
322 #define CONFIG_VIDEO_OMAP3
323 #define LCD_BPP LCD_COLOR16
326 #define CONFIG_SPLASH_SCREEN
327 #define CONFIG_CMD_BMP
328 #define CONFIG_BMP_16BPP
330 #endif /* __CONFIG_H */