3 * Martin Winistoerfer, martinwinistoerfer@gmx.ch.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
26 * Discription: Config header file for cmi
27 * board using an MPC5xx CPU
35 * High Level Configuration Options
38 #define CONFIG_MPC555 1 /* This is an MPC555 CPU */
39 #define CONFIG_CMI 1 /* Using the customized cmi board */
41 #define CONFIG_SYS_TEXT_BASE 0x02000000 /* Boot from flash at location 0x00000000 */
43 /* Serial Console Configuration */
44 #define CONFIG_5xx_CONS_SCI1
45 #undef CONFIG_5xx_CONS_SCI2
47 #define CONFIG_BAUDRATE 57600
53 #define CONFIG_BOOTP_BOOTFILESIZE
54 #define CONFIG_BOOTP_BOOTPATH
55 #define CONFIG_BOOTP_GATEWAY
56 #define CONFIG_BOOTP_HOSTNAME
60 * Command line configuration.
62 #include <config_cmd_default.h>
64 #undef CONFIG_CMD_NET /* disabeled - causes compile errors */
66 #define CONFIG_CMD_MEMORY
67 #define CONFIG_CMD_LOADB
68 #define CONFIG_CMD_REGINFO
69 #define CONFIG_CMD_FLASH
70 #define CONFIG_CMD_LOADS
71 #define CONFIG_CMD_ASKENV
72 #define CONFIG_CMD_BDI
73 #define CONFIG_CMD_CONSOLE
74 #define CONFIG_CMD_SAVEENV
75 #define CONFIG_CMD_RUN
76 #define CONFIG_CMD_IMI
80 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */
82 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
84 #define CONFIG_BOOTCOMMAND "go 02034004" /* autoboot command */
86 #define CONFIG_BOOTARGS "" /* Assuming OS Image in 4 flash sector at offset 4004 */
88 #define CONFIG_WATCHDOG /* turn on platform specific watchdog */
90 #define CONFIG_STATUS_LED 1 /* Enable status led */
92 #define CONFIG_LOADS_ECHO 1 /* Echo on for serial download */
95 * Miscellaneous configurable options
98 #define CONFIG_SYS_LONGHELP /* undef to save memory */
99 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
100 #if defined(CONFIG_CMD_KGDB)
101 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
103 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
105 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
106 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
107 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
109 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
110 #define CONFIG_SYS_MEMTEST_END 0x000fa000 /* 1 MB in SRAM */
112 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
114 #define CONFIG_SYS_HZ 1000 /* Decrementer freq: 1 ms ticks */
116 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 1250000 }
120 * Low Level Configuration Settings
124 * Internal Memory Mapped (This is not the IMMR content)
126 #define CONFIG_SYS_IMMR 0x01000000 /* Physical start adress of internal memory map */
129 * Definitions for initial stack pointer and data area
131 #define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_IMMR + 0x003f9800) /* Physical start adress of internal MPC555 writable RAM */
132 #define CONFIG_SYS_INIT_RAM_SIZE (CONFIG_SYS_IMMR + 0x003fffff) /* Physical end adress of internal MPC555 used RAM area */
133 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_INIT_RAM_ADDR) - GENERATED_GBL_DATA_SIZE) /* Offset from the beginning of ram */
134 #define CONFIG_SYS_INIT_SP_ADDR 0x013fa000 /* Physical start adress of inital stack */
137 * Start addresses for the final memory configuration
138 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
140 #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* Monitor won't change memory map */
141 #define CONFIG_SYS_FLASH_BASE 0x02000000 /* External flash */
142 #define PLD_BASE 0x03000000 /* PLD */
143 #define ANYBUS_BASE 0x03010000 /* Anybus Module */
145 #define CONFIG_SYS_RESET_ADRESS 0x01000000 /* Adress which causes reset */
146 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* CONFIG_SYS_TEXT_BASE is defined in the board config.mk file. */
147 /* This adress is given to the linker with -Ttext to */
148 /* locate the text section at this adress. */
149 #define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
150 #define CONFIG_SYS_MALLOC_LEN (64 << 10) /* Reserve 128 kB for malloc() */
153 * For booting Linux, the board info and command line data
154 * have to be in the first 8 MB of memory, since this is
155 * the maximum mapped by the Linux kernel during initialization.
157 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
160 /*-----------------------------------------------------------------------
162 *-----------------------------------------------------------------------
166 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of memory banks */
167 #define CONFIG_SYS_MAX_FLASH_SECT 64 /* Max number of sectors on one chip */
168 #define CONFIG_SYS_FLASH_ERASE_TOUT 180000 /* Timeout for Flash Erase (in ms) */
169 #define CONFIG_SYS_FLASH_WRITE_TOUT 600 /* Timeout for Flash Write (in ms) */
170 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Physically section protection on */
172 #define CONFIG_ENV_IS_IN_FLASH 1
174 #ifdef CONFIG_ENV_IS_IN_FLASH
175 #define CONFIG_ENV_OFFSET 0x00020000 /* Environment starts at this adress */
176 #define CONFIG_ENV_SIZE 0x00010000 /* Set whole sector as env */
177 #define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
180 /*-----------------------------------------------------------------------
181 * SYPCR - System Protection Control
182 * SYPCR can only be written once after reset!
183 *-----------------------------------------------------------------------
186 #if defined(CONFIG_WATCHDOG)
187 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
188 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
190 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
192 #endif /* CONFIG_WATCHDOG */
194 /*-----------------------------------------------------------------------
195 * TBSCR - Time Base Status and Control
196 *-----------------------------------------------------------------------
197 * Clear Reference Interrupt Status, Timebase freezing enabled
199 #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
201 /*-----------------------------------------------------------------------
202 * PISCR - Periodic Interrupt Status and Control
203 *-----------------------------------------------------------------------
204 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
206 #define CONFIG_SYS_PISCR (PISCR_PITF)
208 /*-----------------------------------------------------------------------
209 * SCCR - System Clock and reset Control Register
210 *-----------------------------------------------------------------------
211 * Set clock output, timebase and RTC source and divider,
212 * power management and some other internal clocks
214 #define SCCR_MASK SCCR_EBDF00
215 #define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_RTDIV | SCCR_RTSEL | \
216 SCCR_COM00 | SCCR_DFNL000 | SCCR_DFNH000)
218 /*-----------------------------------------------------------------------
219 * SIUMCR - SIU Module Configuration
220 *-----------------------------------------------------------------------
223 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00) /* Disable data show cycle */
225 /*-----------------------------------------------------------------------
226 * PLPRCR - PLL, Low-Power, and Reset Control Register
227 *-----------------------------------------------------------------------
228 * Set all bits to 40 Mhz
231 #define CONFIG_SYS_OSC_CLK ((uint)4000000) /* Oscillator clock is 4MHz */
232 #define CONFIG_SYS_PLPRCR (PLPRCR_MF_9 | PLPRCR_DIVF_0)
235 /*-----------------------------------------------------------------------
236 * UMCR - UIMB Module Configuration Register
237 *-----------------------------------------------------------------------
240 #define CONFIG_SYS_UMCR (UMCR_FSPEED) /* IMB clock same as U-bus */
242 /*-----------------------------------------------------------------------
243 * ICTRL - I-Bus Support Control Register
245 #define CONFIG_SYS_ICTRL (ICTRL_ISCT_SER_7) /* Take out of serialized mode */
247 /*-----------------------------------------------------------------------
248 * USIU - Memory Controller Register
249 *-----------------------------------------------------------------------
252 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BR_V | BR_BI | BR_PS_16)
253 #define CONFIG_SYS_OR0_PRELIM (OR_ADDR_MK_FF | OR_SCY_3)
254 #define CONFIG_SYS_BR1_PRELIM (ANYBUS_BASE)
255 #define CONFIG_SYS_OR1_PRELIM (OR_ADDR_MK_FFFF | OR_SCY_1 | OR_ETHR)
256 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_SDRAM_BASE | BR_V | BR_PS_32)
257 #define CONFIG_SYS_OR2_PRELIM (OR_ADDR_MK_FF)
258 #define CONFIG_SYS_BR3_PRELIM (PLD_BASE | BR_V | BR_BI | BR_LBDIR | BR_PS_8)
259 #define CONFIG_SYS_OR3_PRELIM (OR_ADDR_MK_FF | OR_TRLX | OR_BSCY | OR_SCY_8 | \
260 OR_ACS_10 | OR_ETHR | OR_CSNT)
262 #define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* We don't realign the flash */
264 /*-----------------------------------------------------------------------
265 * DER - Timer Decrementer
266 *-----------------------------------------------------------------------
269 #define CONFIG_SYS_DER 0x00000000
271 #endif /* __CONFIG_H */