3 * Murray Jensen <Murray.Jensen@cmst.csiro.au>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * Config header file for Cogent platform using an MPC8xx CPU module
32 * High Level Configuration Options
36 #define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
37 #define CONFIG_COGENT 1 /* using Cogent Modular Architecture */
38 #define CONFIG_CPM2 1 /* Has a CPM2 */
40 #define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */
42 /* Cogent Modular Architecture options */
43 #define CONFIG_CMA282 1 /* ...on a CMA282 CPU module */
44 #define CONFIG_CMA111 1 /* ...on a CMA111 motherboard */
47 * select serial console configuration
49 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
50 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
53 * if CONFIG_CONS_NONE is defined, then the serial console routines must
54 * defined elsewhere (for example, on the cogent platform, there are serial
55 * ports on the motherboard which are used for the serial console - see
56 * cogent/cma101/serial.[ch]).
58 #define CONFIG_CONS_ON_SMC /* define if console on SMC */
59 #undef CONFIG_CONS_ON_SCC /* define if console on SCC */
60 #undef CONFIG_CONS_NONE /* define if console on something else*/
61 #define CONFIG_CONS_INDEX 1 /* which serial channel for console */
62 #undef CONFIG_CONS_USE_EXTC /* SMC/SCC use ext clock not brg_clk */
63 #define CONFIG_CONS_EXTC_RATE 3686400 /* SMC/SCC ext clk rate in Hz */
64 #define CONFIG_CONS_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/
67 * select ethernet configuration
69 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
70 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
73 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
74 * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
75 * from CONFIG_COMMANDS to remove support for networking.
77 #undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
78 #undef CONFIG_ETHER_ON_FCC /* define if ether on FCC */
79 #define CONFIG_ETHER_NONE /* define if ether on something else */
80 #define CONFIG_ETHER_INDEX 1 /* which channel for ether */
82 /* system clock rate (CLKIN) - equal to the 60x and local bus speed */
83 #define CONFIG_8260_CLKIN 66666666 /* in Hz */
85 #if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
86 #define CONFIG_BAUDRATE 230400
88 #define CONFIG_BAUDRATE 9600
93 * Command line configuration.
95 #include <config_cmd_default.h>
97 #define CONFIG_CMD_KGDB
103 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */
105 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
107 #define CONFIG_BOOTCOMMAND "bootm 04080000 04200000" /* autoboot command*/
109 #define CONFIG_BOOTARGS "root=/dev/ram rw"
111 #if defined(CONFIG_CMD_KGDB)
112 #define CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
113 #undef CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
114 #undef CONFIG_KGDB_NONE /* define if kgdb on something else */
115 #define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */
116 #define CONFIG_KGDB_USE_EXTC /* SMC/SCC use ext clock not brg_clk */
117 #define CONFIG_KGDB_EXTC_RATE 3686400 /* serial ext clk rate in Hz */
118 #define CONFIG_KGDB_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/
119 # if defined(CONFIG_KGDB_NONE) || defined(CONFIG_KGDB_USE_EXTC)
120 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port at */
122 #define CONFIG_KGDB_BAUDRATE 9600 /* speed to run kgdb serial port at */
126 #undef CONFIG_WATCHDOG /* disable platform specific watchdog */
129 * Miscellaneous configurable options
131 #define CFG_LONGHELP /* undef to save memory */
132 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
133 #if defined(CONFIG_CMD_KGDB)
134 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
136 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
138 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
139 #define CFG_MAXARGS 16 /* max number of command args */
140 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
142 #define CFG_MEMTEST_START 0x00400000 /* memtest works on */
143 #define CFG_MEMTEST_END 0x01c00000 /* 4 ... 28 MB in DRAM */
145 #define CFG_LOAD_ADDR 0x100000 /* default load address */
147 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
149 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
152 * Low Level Configuration Settings
153 * (address mappings, register initial values, etc.)
154 * You should know what you are doing if you make changes here.
157 /*-----------------------------------------------------------------------
158 * Low Level Cogent settings
159 * if CFG_CMA_CONS_SERIAL is defined, make sure the 8260 CPM serial is not.
160 * also, make sure CONFIG_CONS_INDEX is still defined - the index will be
161 * 1 for serialA, 2 for serialB, 3 for ser2A, 4 for ser2B
162 * (second 2 for CMA120 only)
164 #define CFG_CMA_MB_BASE 0x00000000 /* base of m/b address space */
166 #include <configs/cogent_common.h>
168 #ifdef CONFIG_CONS_NONE
169 #define CFG_CMA_CONS_SERIAL /* use Cogent motherboard serial for console */
171 #define CFG_CMA_LCD_HEARTBEAT /* define for sec rotator in lcd corner */
172 #define CONFIG_SHOW_ACTIVITY
174 #if (CMA_MB_CAPS & CMA_MB_CAP_FLASH)
176 * flash exists on the motherboard
177 * set these four according to TOP dipsw:
178 * TOP on => ..._FLLOW_... (boot EPROM space is high so FLASH is low )
179 * TOP off => ..._FLHIGH_... (boot EPROM space is low so FLASH is high)
181 #define CMA_MB_FLASH_EXEC_BASE CMA_MB_FLLOW_EXEC_BASE
182 #define CMA_MB_FLASH_EXEC_SIZE CMA_MB_FLLOW_EXEC_SIZE
183 #define CMA_MB_FLASH_RDWR_BASE CMA_MB_FLLOW_RDWR_BASE
184 #define CMA_MB_FLASH_RDWR_SIZE CMA_MB_FLLOW_RDWR_SIZE
186 #define CMA_MB_FLASH_BASE CMA_MB_FLASH_EXEC_BASE
187 #define CMA_MB_FLASH_SIZE CMA_MB_FLASH_EXEC_SIZE
189 /*-----------------------------------------------------------------------
190 * Hard Reset Configuration Words
192 * if you change bits in the HRCW, you must also change the CFG_*
193 * defines for the various registers affected by the HRCW e.g. changing
194 * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
196 #define CFG_HRCW_MASTER (HRCW_EBM|HRCW_BPS10|HRCW_L2CPC10|HRCW_DPPC11|\
197 HRCW_ISB100|HRCW_MMR11|HRCW_MODCK_H0101)
198 /* no slaves so just duplicate the master hrcw */
199 #define CFG_HRCW_SLAVE1 CFG_HRCW_MASTER
200 #define CFG_HRCW_SLAVE2 CFG_HRCW_MASTER
201 #define CFG_HRCW_SLAVE3 CFG_HRCW_MASTER
202 #define CFG_HRCW_SLAVE4 CFG_HRCW_MASTER
203 #define CFG_HRCW_SLAVE5 CFG_HRCW_MASTER
204 #define CFG_HRCW_SLAVE6 CFG_HRCW_MASTER
205 #define CFG_HRCW_SLAVE7 CFG_HRCW_MASTER
207 /*-----------------------------------------------------------------------
208 * Internal Memory Mapped Register
210 #define CFG_IMMR 0xF0000000
212 /*-----------------------------------------------------------------------
213 * Definitions for initial stack pointer and data area (in DPRAM)
215 #define CFG_INIT_RAM_ADDR CFG_IMMR
216 #define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
217 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
218 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
219 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
221 /*-----------------------------------------------------------------------
222 * Start addresses for the final memory configuration
223 * (Set up by the startup code)
224 * Please note that CFG_SDRAM_BASE _must_ start at 0
226 #define CFG_SDRAM_BASE CMA_MB_RAM_BASE
228 #define CFG_FLASH_BASE CMA_MB_SLOT2_BASE /* cma302 in slot 2 */
230 #define CFG_FLASH_BASE CMA_MB_FLASH_BASE /* flash on m/b */
232 #define CFG_MONITOR_BASE TEXT_BASE
233 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
234 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
237 * For booting Linux, the board info and command line data
238 * have to be in the first 8 MB of memory, since this is
239 * the maximum mapped by the Linux kernel during initialization.
241 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Mem map for Linux*/
243 /*-----------------------------------------------------------------------
246 #define CFG_MAX_FLASH_BANKS 2 /* max num of memory banks */
247 #define CFG_MAX_FLASH_SECT 67 /* max num of sects on one chip */
249 #define CFG_FLASH_ERASE_TOUT 120000 /* Flash Erase Timeout (in ms) */
250 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
252 #define CFG_ENV_IS_IN_FLASH 1
253 #define CFG_ENV_ADDR CFG_FLASH_BASE /* Addr of Environment Sector */
255 #define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
256 #define CFG_ENV_SECT_SIZE (512*1024) /* see README - env sect real size */
258 #define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
261 /*-----------------------------------------------------------------------
262 * Cache Configuration
264 #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
265 #if defined(CONFIG_CMD_KGDB)
266 # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value*/
269 /*-----------------------------------------------------------------------
270 * HIDx - Hardware Implementation-dependent Registers 2-11
271 *-----------------------------------------------------------------------
272 * HID0 also contains cache control - initially enable both caches and
273 * invalidate contents, then the final state leaves only the instruction
274 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
275 * but Soft reset does not.
277 * HID1 has only read-only information - nothing to set.
279 #define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
281 #define CFG_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE)
284 /*-----------------------------------------------------------------------
285 * RMR - Reset Mode Register 5-5
286 *-----------------------------------------------------------------------
287 * turn on Checkstop Reset Enable
289 #define CFG_RMR RMR_CSRE
291 /*-----------------------------------------------------------------------
292 * BCR - Bus Configuration 4-25
293 *-----------------------------------------------------------------------
295 #define CFG_BCR BCR_EBM
297 /*-----------------------------------------------------------------------
298 * SIUMCR - SIU Module Configuration 4-31
299 *-----------------------------------------------------------------------
301 #define CFG_SIUMCR (SIUMCR_DPPC11|SIUMCR_L2CPC10|SIUMCR_MMR11)
303 /*-----------------------------------------------------------------------
304 * SYPCR - System Protection Control 4-35
305 * SYPCR can only be written once after reset!
306 *-----------------------------------------------------------------------
307 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
309 #if defined(CONFIG_WATCHDOG)
310 #define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
311 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
313 #define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
314 SYPCR_SWRI|SYPCR_SWP)
315 #endif /* CONFIG_WATCHDOG */
317 /*-----------------------------------------------------------------------
318 * TMCNTSC - Time Counter Status and Control 4-40
319 *-----------------------------------------------------------------------
320 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
321 * and enable Time Counter
323 #define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
325 /*-----------------------------------------------------------------------
326 * PISCR - Periodic Interrupt Status and Control 4-42
327 *-----------------------------------------------------------------------
328 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
331 #define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
333 /*-----------------------------------------------------------------------
334 * SCCR - System Clock Control 9-8
335 *-----------------------------------------------------------------------
336 * Ensure DFBRG is Divide by 16
338 #define CFG_SCCR (SCCR_DFBRG01)
340 /*-----------------------------------------------------------------------
341 * RCCR - RISC Controller Configuration 13-7
342 *-----------------------------------------------------------------------
346 #if defined(CONFIG_CMA282)
349 * Init Memory Controller:
351 * According to the Cogent manual, only CS0 and CS2 are used - CS0 for EPROM
352 * and CS2 for (optional) local bus RAM on the CPU module.
354 * Note the motherboard address space (256 Mbyte in size) is connected
355 * to the 60x Bus and is located starting at address 0. The Hard Reset
356 * Configuration Word should put the 60x Bus into External Bus Mode, since
357 * we dont set up any memory controller maps for it (see BCR[EBM], 4-26).
359 * (the *_SIZE vars must be a power of 2)
362 #define CFG_CMA_CS0_BASE TEXT_BASE /* EPROM */
363 #define CFG_CMA_CS0_SIZE (1 << 20)
365 #define CFG_CMA_CS2_BASE 0x10000000 /* Local Bus SDRAM */
366 #define CFG_CMA_CS2_SIZE (16 << 20)
370 * CS0 maps the EPROM on the cpu module
371 * Set it for 10 wait states, address CFG_MONITOR_BASE and size 1M
373 * Note: We must have already transferred control to the final location
374 * of the EPROM before these are used, because when BR0/OR0 are set, the
375 * mirror of the eprom at any other addresses will disappear.
378 /* base address = CFG_CMA_CS0_BASE, 16-bit, no parity, r/o, gpcm (60x bus) */
379 #define CFG_BR0_PRELIM ((CFG_CMA_CS0_BASE&BRx_BA_MSK)|BRx_PS_16|BRx_WP|BRx_V)
380 /* mask size CFG_CMA_CS0_SIZE, csneg 1/4 early, adr-to-cs 1/2, 10-wait states */
381 #define CFG_OR0_PRELIM (P2SZ_TO_AM(CFG_CMA_CS0_SIZE)|\
382 ORxG_CSNT|ORxG_ACS_DIV2|ORxG_SCY_10_CLK)
385 * CS2 enables the Local Bus SDRAM on the CPU Module
387 * Will leave this unset for the moment, because a) my CPU module has no
388 * SDRAM installed (it is optional); and b) it will require programming
389 * one of the UPMs in SDRAM mode - not a trivial job, and hard to get right
390 * if you can't test it.
394 /* base address = CFG_CMA_CS2_BASE, 32-bit, no parity, ??? */
395 #define CFG_BR0_PRELIM ((CFG_CMA_CS2_BASE&BRx_BA_MSK)|BRx_PS_32|/*???*/|BRx_V)
396 /* mask size CFG_CMA_CS2_SIZE, CS time normal, ??? */
397 #define CFG_OR2_PRELIM ((~(CFG_CMA_CS2_SIZE-1)&ORx_AM_MSK)|/*???*/)
403 * Internal Definitions
407 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/
408 #define BOOTFLAG_WARM 0x02 /* Software reboot */
410 #endif /* __CONFIG_H */