3 * Murray Jensen <Murray.Jensen@cmst.csiro.au>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * Config header file for Cogent platform using an MPC8xx CPU module
32 * High Level Configuration Options
36 #define CONFIG_MPC860 1 /* This is an MPC860 CPU */
37 #define CONFIG_COGENT 1 /* using Cogent Modular Architecture */
39 #define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */
41 /* Cogent Modular Architecture options */
42 #define CONFIG_CMA286_60_OLD 1 /* ...on an old CMA286-60 CPU module */
43 #define CONFIG_CMA102 1 /* ...on a CMA102 motherboard */
44 #define CONFIG_CMA302 1 /* ...with a CMA302 flash I/O module */
46 /* serial console configuration */
47 #undef CONFIG_8xx_CONS_SMC1
48 #undef CONFIG_8xx_CONS_SMC2
49 #define CONFIG_8xx_CONS_NONE /* not on 8xx serial ports (eg on cogent m/b) */
51 #if defined(CONFIG_CMA286_60_OLD)
52 #define CONFIG_8xx_GCLK_FREQ 33333000 /* define if cant use get_gclk_freq */
55 #define CONFIG_BAUDRATE 230400
57 #define CONFIG_HARD_I2C /* I2C with hardware support */
58 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
59 #define CFG_I2C_SLAVE 0x7F
63 * Command line configuration.
65 #include <config_cmd_default.h>
67 #define CONFIG_CMD_KGDB
68 #define CONFIG_CMD_I2C
74 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */
76 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
78 #define CONFIG_BOOTCOMMAND "bootm 04080000 04200000" /* autoboot command*/
80 #define CONFIG_BOOTARGS "root=/dev/ram rw"
82 #if defined(CONFIG_CMD_KGDB)
83 #undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
84 #undef CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
85 #define CONFIG_KGDB_NONE /* define if kgdb on something else */
86 #define CONFIG_KGDB_INDEX 2 /* which SMC/SCC channel for kgdb */
87 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
90 #define CONFIG_WATCHDOG /* turn on platform specific watchdog */
93 * Miscellaneous configurable options
95 #define CFG_LONGHELP /* undef to save memory */
96 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
97 #if defined(CONFIG_CMD_KGDB)
98 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
100 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
102 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
103 #define CFG_MAXARGS 16 /* max number of command args */
104 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
106 #define CFG_MEMTEST_START 0x00400000 /* memtest works on */
107 #define CFG_MEMTEST_END 0x01c00000 /* 4 ... 28 MB in DRAM */
109 #define CFG_LOAD_ADDR 0x100000 /* default load address */
111 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
113 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
115 #define CFG_ALLOC_DPRAM
118 * Low Level Configuration Settings
119 * (address mappings, register initial values, etc.)
120 * You should know what you are doing if you make changes here.
123 /*-----------------------------------------------------------------------
124 * Low Level Cogent settings
125 * if CFG_CMA_CONS_SERIAL is defined, make sure the 8xx CPM serial is not.
126 * also, make sure CONFIG_CONS_INDEX is still defined - the index will be
127 * 1 for serialA, 2 for serialB, 3 for ser2A, 4 for ser2B
128 * (second 2 for CMA120 only)
130 #define CFG_CMA_MB_BASE 0x00000000 /* base of m/b address space */
132 #include <configs/cogent_common.h>
134 #define CFG_CMA_CONS_SERIAL /* use Cogent motherboard serial for console */
135 #define CONFIG_CONS_INDEX 1
136 #define CFG_CMA_LCD_HEARTBEAT /* define for sec rotator in lcd corner */
137 #define CONFIG_SHOW_ACTIVITY
138 #if (CMA_MB_CAPS & CMA_MB_CAP_FLASH)
140 * flash exists on the motherboard
141 * set these four according to TOP dipsw:
142 * TOP on => ..._FLLOW_... (boot EPROM space is high so FLASH is low )
143 * TOP off => ..._FLHIGH_... (boot EPROM space is low so FLASH is high)
145 #define CMA_MB_FLASH_EXEC_BASE CMA_MB_FLLOW_EXEC_BASE
146 #define CMA_MB_FLASH_EXEC_SIZE CMA_MB_FLLOW_EXEC_SIZE
147 #define CMA_MB_FLASH_RDWR_BASE CMA_MB_FLLOW_RDWR_BASE
148 #define CMA_MB_FLASH_RDWR_SIZE CMA_MB_FLLOW_RDWR_SIZE
150 #define CMA_MB_FLASH_BASE CMA_MB_FLASH_EXEC_BASE
151 #define CMA_MB_FLASH_SIZE CMA_MB_FLASH_EXEC_SIZE
153 /*-----------------------------------------------------------------------
154 * Internal Memory Mapped Register
156 #define CFG_IMMR 0xFF000000
158 /*-----------------------------------------------------------------------
159 * Definitions for initial stack pointer and data area (in DPRAM)
161 #define CFG_INIT_RAM_ADDR CFG_IMMR
162 #define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
163 #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
164 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
165 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
167 /*-----------------------------------------------------------------------
168 * Start addresses for the final memory configuration
169 * (Set up by the startup code)
170 * Please note that CFG_SDRAM_BASE _must_ start at 0
172 #define CFG_SDRAM_BASE CMA_MB_RAM_BASE
174 #define CFG_FLASH_BASE CMA_MB_SLOT2_BASE /* cma302 in slot 2 */
176 #define CFG_FLASH_BASE CMA_MB_FLASH_BASE /* flash on m/b */
178 #define CFG_MONITOR_BASE TEXT_BASE
179 #define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
180 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
183 * For booting Linux, the board info and command line data
184 * have to be in the first 8 MB of memory, since this is
185 * the maximum mapped by the Linux kernel during initialization.
187 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
188 /*-----------------------------------------------------------------------
191 #define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
192 #define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
194 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
195 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
197 #define CFG_ENV_IS_IN_FLASH 1
198 #define CFG_ENV_ADDR CFG_FLASH_BASE /* Addr of Environment Sector */
200 #define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
201 #define CFG_ENV_SECT_SIZE (512*1024) /* see README - env sect real size */
203 #define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
205 /*-----------------------------------------------------------------------
206 * Cache Configuration
208 #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
209 #if defined(CONFIG_CMD_KGDB)
210 #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
214 /*-----------------------------------------------------------------------
215 * SYPCR - System Protection Control 11-9
216 * SYPCR can only be written once after reset!
217 *-----------------------------------------------------------------------
218 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
220 #if defined(CONFIG_WATCHDOG)
221 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
222 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
224 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
225 #endif /* CONFIG_WATCHDOG */
227 /*-----------------------------------------------------------------------
228 * SIUMCR - SIU Module Configuration 11-6
229 *-----------------------------------------------------------------------
230 * PCMCIA config., multi-function pin tri-state
232 #define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
234 /*-----------------------------------------------------------------------
235 * TBSCR - Time Base Status and Control 11-26
236 *-----------------------------------------------------------------------
237 * Clear Reference Interrupt Status, Timebase freezing enabled
239 #define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
241 /*-----------------------------------------------------------------------
242 * PISCR - Periodic Interrupt Status and Control 11-31
243 *-----------------------------------------------------------------------
244 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
246 #define CFG_PISCR (PISCR_PS | PISCR_PITF)
248 /*-----------------------------------------------------------------------
249 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
250 *-----------------------------------------------------------------------
251 * Reset PLL lock status sticky bit, timer expired status bit and timer
252 * interrupt status bit - leave PLL multiplication factor unchanged !
254 #define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
256 /*-----------------------------------------------------------------------
257 * SCCR - System Clock and reset Control Register 15-27
258 *-----------------------------------------------------------------------
259 * Set clock output, timebase and RTC source and divider,
260 * power management and some other internal clocks
262 #define SCCR_MASK SCCR_EBDF11
263 #define CFG_SCCR (SCCR_TBS | SCCR_RTDIV | SCCR_RTSEL | \
264 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
265 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
268 /*-----------------------------------------------------------------------
270 *-----------------------------------------------------------------------
273 #define CFG_PCMCIA_MEM_ADDR (0xE0000000)
274 #define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
275 #define CFG_PCMCIA_DMA_ADDR (0xE4000000)
276 #define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
277 #define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
278 #define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
279 #define CFG_PCMCIA_IO_ADDR (0xEC000000)
280 #define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
282 /*-----------------------------------------------------------------------
284 *-----------------------------------------------------------------------
287 /*#define CFG_DER 0x2002000F*/
290 #if defined(CONFIG_CMA286_60_OLD)
293 * Init Memory Controller:
295 * NOTE: although the names (CFG_xRn_PRELIM) suggest preliminary settings,
296 * they are actually the final settings for this cpu/board, because the
297 * flash and RAM are on the motherboard, accessed via the CMAbus, and the
298 * mappings are pretty much fixed.
300 * (the *_SIZE vars must be a power of 2)
303 #define CFG_CMA_CS0_BASE TEXT_BASE /* EPROM */
304 #define CFG_CMA_CS0_SIZE (1 << 20)
305 #define CFG_CMA_CS1_BASE CMA_MB_RAM_BASE /* RAM + I/O SLOT 1 */
306 #define CFG_CMA_CS1_SIZE (64 << 20)
307 #define CFG_CMA_CS2_BASE CMA_MB_SLOT2_BASE /* I/O SLOTS 2 + 3 */
308 #define CFG_CMA_CS2_SIZE (64 << 20)
309 #define CFG_CMA_CS3_BASE CMA_MB_ROMLOW_BASE /* M/B I/O */
310 #define CFG_CMA_CS3_SIZE (32 << 20)
313 * CS0 maps the EPROM on the cpu module
314 * Set it for 4 wait states, address CFG_MONITOR_BASE and size 1M
316 * Note: We must have already transferred control to the final location
317 * of the EPROM before these are used, because when BR0/OR0 are set, the
318 * mirror of the eprom at any other addresses will disappear.
321 /* base address = CFG_CMA_CS0_BASE, 16-bit, no parity, r/o, gpcm */
322 #define CFG_BR0_PRELIM ((CFG_CMA_CS0_BASE&BR_BA_MSK)|BR_PS_16|BR_WP|BR_V)
323 /* mask size CFG_CMA_CS0_SIZE, CS time normal, burst inhibit, 4-wait states */
324 #define CFG_OR0_PRELIM ((~(CFG_CMA_CS0_SIZE-1)&OR_AM_MSK)|OR_BI|OR_SCY_4_CLK)
327 * CS1 maps motherboard DRAM and motherboard I/O slot 1
328 * (each 32Mbyte in size)
331 /* base address = CFG_CMA_CS1_BASE, 32-bit, no parity, r/w, gpcm */
332 #define CFG_BR1_PRELIM ((CFG_CMA_CS1_BASE&BR_BA_MSK)|BR_V)
333 /* mask size CFG_CMA_CS1_SIZE, CS time normal, burst ok, ext xfer ack */
334 #define CFG_OR1_PRELIM ((~(CFG_CMA_CS1_SIZE-1)&OR_AM_MSK)|OR_SETA)
337 * CS2 maps motherboard I/O slots 2 and 3
338 * (each 32Mbyte in size)
341 /* base address = CFG_CMA_CS2_BASE, 32-bit, no parity, r/w, gpcm */
342 #define CFG_BR2_PRELIM ((CFG_CMA_CS2_BASE&BR_BA_MSK)|BR_V)
343 /* mask size CFG_CMA_CS2_SIZE, CS time normal, burst ok, ext xfer ack */
344 #define CFG_OR2_PRELIM ((~(CFG_CMA_CS2_SIZE-1)&OR_AM_MSK)|OR_SETA)
347 * CS3 maps motherboard I/O
351 /* base address = CFG_CMA_CS3_BASE, 32-bit, no parity, r/w, gpcm */
352 #define CFG_BR3_PRELIM ((CFG_CMA_CS3_BASE&BR_BA_MSK)|BR_V)
353 /* mask size CFG_CMA_CS3_SIZE, CS time normal, burst inhibit, ext xfer ack */
354 #define CFG_OR3_PRELIM ((~(CFG_CMA_CS3_SIZE-1)&OR_AM_MSK)|OR_BI|OR_SETA)
359 * Internal Definitions
363 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
364 #define BOOTFLAG_WARM 0x02 /* Software reboot */
366 #endif /* __CONFIG_H */