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[u-boot] / include / configs / colibri_pxa270.h
1 /*
2  * Toradex Colibri PXA270 configuration file
3  *
4  * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
5  * Copyright (C) 2015-2016 Marcel Ziswiler <marcel@ziswiler.com>
6  *
7  * SPDX-License-Identifier:     GPL-2.0+
8  */
9
10 #ifndef __CONFIG_H
11 #define __CONFIG_H
12
13 /*
14  * High Level Board Configuration Options
15  */
16 #define CONFIG_CPU_PXA27X               1       /* Marvell PXA270 CPU */
17 #define CONFIG_SYS_TEXT_BASE            0x0
18 /* Avoid overwriting factory configuration block */
19 #define CONFIG_BOARD_SIZE_LIMIT         0x40000
20
21 /* We will never enable dcache because we have to setup MMU first */
22 #define CONFIG_SYS_DCACHE_OFF
23
24 #define CONFIG_DISPLAY_BOARDINFO_LATE   /* Calls show_board_info() */
25
26 /*
27  * Environment settings
28  */
29 #define CONFIG_ENV_OVERWRITE
30 #define CONFIG_ENV_VARS_UBOOT_CONFIG
31 #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
32 #define CONFIG_SYS_MALLOC_LEN           (128 * 1024)
33 #define CONFIG_ARCH_CPU_INIT
34 #define CONFIG_BOOTCOMMAND                                              \
35         "if fatload mmc 0 0xa0000000 uImage; then "                     \
36                 "bootm 0xa0000000; "                                    \
37         "fi; "                                                          \
38         "if usb reset && fatload usb 0 0xa0000000 uImage; then "        \
39                 "bootm 0xa0000000; "                                    \
40         "fi; "                                                          \
41         "bootm 0xc0000;"
42 #define CONFIG_TIMESTAMP
43 #define CONFIG_CMDLINE_TAG
44 #define CONFIG_SETUP_MEMORY_TAGS
45
46 /*
47  * Serial Console Configuration
48  */
49
50 /*
51  * Bootloader Components Configuration
52  */
53
54 /* I2C support */
55 #ifdef CONFIG_SYS_I2C
56 #define CONFIG_SYS_I2C_PXA
57 #define CONFIG_PXA_STD_I2C
58 #define CONFIG_PXA_PWR_I2C
59 #define CONFIG_SYS_I2C_SPEED            100000
60 #endif
61
62 /* LCD support */
63 #ifdef CONFIG_LCD
64 #define CONFIG_PXA_LCD
65 #define CONFIG_PXA_VGA
66 #define CONFIG_LCD_LOGO
67 #endif
68
69 /*
70  * Networking Configuration
71  */
72 #ifdef  CONFIG_CMD_NET
73
74 #define CONFIG_DRIVER_DM9000            1
75 #define CONFIG_DM9000_BASE              0x08000000
76 #define DM9000_IO                       (CONFIG_DM9000_BASE)
77 #define DM9000_DATA                     (CONFIG_DM9000_BASE + 4)
78 #define CONFIG_NET_RETRY_COUNT          10
79
80 #define CONFIG_BOOTP_BOOTFILESIZE
81 #define CONFIG_BOOTP_BOOTPATH
82 #define CONFIG_BOOTP_GATEWAY
83 #define CONFIG_BOOTP_HOSTNAME
84 #endif
85
86 #undef  CONFIG_SYS_LONGHELP             /* Saves 10 KB */
87 #define CONFIG_SYS_PBSIZE               \
88         (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
89 #define CONFIG_SYS_MAXARGS              16
90 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
91 #define CONFIG_SYS_DEVICE_NULLDEV       1
92 #undef  CONFIG_CMDLINE_EDITING          /* Saves 2.5 KB */
93 #undef  CONFIG_AUTO_COMPLETE            /* Saves 2.5 KB */
94
95 /*
96  * Clock Configuration
97  */
98 #define CONFIG_SYS_CPUSPEED             0x290           /* 520MHz */
99
100 /*
101  * DRAM Map
102  */
103 #define CONFIG_NR_DRAM_BANKS            1               /* We have 1 bank of DRAM */
104 #define PHYS_SDRAM_1                    0xa0000000      /* SDRAM Bank #1 */
105 #define PHYS_SDRAM_1_SIZE               0x04000000      /* 64 MB */
106
107 #define CONFIG_SYS_DRAM_BASE            0xa0000000      /* CS0 */
108 #define CONFIG_SYS_DRAM_SIZE            0x04000000      /* 64 MB DRAM */
109
110 #define CONFIG_SYS_MEMTEST_START        0xa0400000      /* memtest works on */
111 #define CONFIG_SYS_MEMTEST_END          0xa0800000      /* 4 ... 8 MB in DRAM */
112
113 #define CONFIG_SYS_LOAD_ADDR            PHYS_SDRAM_1
114 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
115 #define CONFIG_SYS_INIT_SP_ADDR         0x5c010000
116
117 /*
118  * NOR FLASH
119  */
120 #ifdef  CONFIG_CMD_FLASH
121 #define PHYS_FLASH_1                    0x00000000      /* Flash Bank #1 */
122 #define PHYS_FLASH_SIZE                 0x02000000      /* 32 MB */
123 #define CONFIG_SYS_FLASH_BASE           PHYS_FLASH_1
124
125 #define CONFIG_SYS_FLASH_CFI
126 #define CONFIG_FLASH_CFI_DRIVER         1
127 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_32BIT
128
129 #define CONFIG_SYS_MAX_FLASH_SECT       (4 + 255)
130 #define CONFIG_SYS_MAX_FLASH_BANKS      1
131
132 #define CONFIG_SYS_FLASH_ERASE_TOUT     (25 * CONFIG_SYS_HZ)
133 #define CONFIG_SYS_FLASH_WRITE_TOUT     (25 * CONFIG_SYS_HZ)
134 #define CONFIG_SYS_FLASH_LOCK_TOUT      (25 * CONFIG_SYS_HZ)
135 #define CONFIG_SYS_FLASH_UNLOCK_TOUT    (25 * CONFIG_SYS_HZ)
136
137 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE       1
138 #define CONFIG_SYS_FLASH_PROTECTION             1
139 #endif
140
141 #define CONFIG_SYS_MONITOR_BASE         0x0
142 #define CONFIG_SYS_MONITOR_LEN          0x40000
143
144 /* Skip factory configuration block */
145 #define CONFIG_ENV_ADDR                 \
146                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN + 0x40000)
147 #define CONFIG_ENV_SIZE                 0x40000
148 #define CONFIG_ENV_SECT_SIZE            0x40000
149
150 /*
151  * GPIO settings
152  */
153 #define CONFIG_SYS_GPSR0_VAL    0x00000000
154 #define CONFIG_SYS_GPSR1_VAL    0x00020000
155 #define CONFIG_SYS_GPSR2_VAL    0x0002c000
156 #define CONFIG_SYS_GPSR3_VAL    0x00000000
157
158 #define CONFIG_SYS_GPCR0_VAL    0x00000000
159 #define CONFIG_SYS_GPCR1_VAL    0x00000000
160 #define CONFIG_SYS_GPCR2_VAL    0x00000000
161 #define CONFIG_SYS_GPCR3_VAL    0x00000000
162
163 #define CONFIG_SYS_GPDR0_VAL    0xc8008000
164 #define CONFIG_SYS_GPDR1_VAL    0xfc02a981
165 #define CONFIG_SYS_GPDR2_VAL    0x92c3ffff
166 #define CONFIG_SYS_GPDR3_VAL    0x0061e804
167
168 #define CONFIG_SYS_GAFR0_L_VAL  0x80100000
169 #define CONFIG_SYS_GAFR0_U_VAL  0xa5c00010
170 #define CONFIG_SYS_GAFR1_L_VAL  0x6992901a
171 #define CONFIG_SYS_GAFR1_U_VAL  0xaaa50008
172 #define CONFIG_SYS_GAFR2_L_VAL  0xaaaaaaaa
173 #define CONFIG_SYS_GAFR2_U_VAL  0x4109a002
174 #define CONFIG_SYS_GAFR3_L_VAL  0x54000310
175 #define CONFIG_SYS_GAFR3_U_VAL  0x00005401
176
177 #define CONFIG_SYS_PSSR_VAL     0x30
178
179 /*
180  * Clock settings
181  */
182 #define CONFIG_SYS_CKEN         0x00500240
183 #define CONFIG_SYS_CCCR         0x02000290
184
185 /*
186  * Memory settings
187  */
188 #define CONFIG_SYS_MSC0_VAL     0x9ee1c5f2
189 #define CONFIG_SYS_MSC1_VAL     0x9ee1f994
190 #define CONFIG_SYS_MSC2_VAL     0x9ee19ee1
191 #define CONFIG_SYS_MDCNFG_VAL   0x090009c9
192 #define CONFIG_SYS_MDREFR_VAL   0x2003a031
193 #define CONFIG_SYS_MDMRS_VAL    0x00220022
194 #define CONFIG_SYS_FLYCNFG_VAL  0x00010001
195 #define CONFIG_SYS_SXCNFG_VAL   0x40044004
196
197 /*
198  * PCMCIA and CF Interfaces
199  */
200 #define CONFIG_SYS_MECR_VAL     0x00000000
201 #define CONFIG_SYS_MCMEM0_VAL   0x00028307
202 #define CONFIG_SYS_MCMEM1_VAL   0x00014307
203 #define CONFIG_SYS_MCATT0_VAL   0x00038787
204 #define CONFIG_SYS_MCATT1_VAL   0x0001c787
205 #define CONFIG_SYS_MCIO0_VAL    0x0002830f
206 #define CONFIG_SYS_MCIO1_VAL    0x0001430f
207
208 #include "pxa-common.h"
209
210 #endif /* __CONFIG_H */