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1 /*
2  * Toradex Colibri PXA270 configuration file
3  *
4  * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
5  * Copyright (C) 2015 Marcel Ziswiler <marcel@ziswiler.com>
6  *
7  * SPDX-License-Identifier:     GPL-2.0+
8  */
9
10 #ifndef __CONFIG_H
11 #define __CONFIG_H
12
13 /*
14  * High Level Board Configuration Options
15  */
16 #define CONFIG_CPU_PXA27X               1       /* Marvell PXA270 CPU */
17 #define CONFIG_SYS_TEXT_BASE            0x0
18 /* Avoid overwriting factory configuration block */
19 #define CONFIG_BOARD_SIZE_LIMIT         0x40000
20
21 /* We will never enable dcache because we have to setup MMU first */
22 #define CONFIG_SYS_DCACHE_OFF
23
24 /*
25  * Environment settings
26  */
27 #define CONFIG_ENV_OVERWRITE
28 #define CONFIG_SYS_MALLOC_LEN           (128 * 1024)
29 #define CONFIG_ARCH_CPU_INIT
30 #define CONFIG_BOOTCOMMAND                                              \
31         "if fatload mmc 0 0xa0000000 uImage; then "                     \
32                 "bootm 0xa0000000; "                                    \
33         "fi; "                                                          \
34         "if usb reset && fatload usb 0 0xa0000000 uImage; then "        \
35                 "bootm 0xa0000000; "                                    \
36         "fi; "                                                          \
37         "bootm 0xc0000;"
38 #define CONFIG_BOOTARGS                 "console=tty0 console=ttyS0,115200"
39 #define CONFIG_TIMESTAMP
40 #define CONFIG_CMDLINE_TAG
41 #define CONFIG_SETUP_MEMORY_TAGS
42
43 /*
44  * Serial Console Configuration
45  */
46 #define CONFIG_FFUART                   1
47 #define CONFIG_CONS_INDEX               3
48 #define CONFIG_BAUDRATE                 115200
49
50 /*
51  * Bootloader Components Configuration
52  */
53 #define CONFIG_CMD_ENV
54
55 /* I2C support */
56 #ifdef CONFIG_SYS_I2C
57 #define CONFIG_SYS_I2C_PXA
58 #define CONFIG_PXA_STD_I2C
59 #define CONFIG_PXA_PWR_I2C
60 #define CONFIG_SYS_I2C_SPEED            100000
61 #endif
62
63 /* LCD support */
64 #ifdef CONFIG_LCD
65 #define CONFIG_PXA_LCD
66 #define CONFIG_PXA_VGA
67 #define CONFIG_SYS_WHITE_ON_BLACK
68 #define CONFIG_CMD_BMP
69 #define CONFIG_LCD_LOGO
70 #endif
71
72 /*
73  * Networking Configuration
74  */
75 #ifdef  CONFIG_CMD_NET
76
77 #define CONFIG_DRIVER_DM9000            1
78 #define CONFIG_DM9000_BASE              0x08000000
79 #define DM9000_IO                       (CONFIG_DM9000_BASE)
80 #define DM9000_DATA                     (CONFIG_DM9000_BASE + 4)
81 #define CONFIG_NET_RETRY_COUNT          10
82
83 #define CONFIG_BOOTP_BOOTFILESIZE
84 #define CONFIG_BOOTP_BOOTPATH
85 #define CONFIG_BOOTP_GATEWAY
86 #define CONFIG_BOOTP_HOSTNAME
87 #endif
88
89 #undef  CONFIG_SYS_LONGHELP             /* Saves 10 KB */
90 #define CONFIG_SYS_CBSIZE               256
91 #define CONFIG_SYS_PBSIZE               \
92         (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
93 #define CONFIG_SYS_MAXARGS              16
94 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
95 #define CONFIG_SYS_DEVICE_NULLDEV       1
96 #define CONFIG_CMDLINE_EDITING          1
97 #define CONFIG_AUTO_COMPLETE            1
98
99 /*
100  * Clock Configuration
101  */
102 #define CONFIG_SYS_CPUSPEED             0x290           /* 520MHz */
103
104 /*
105  * DRAM Map
106  */
107 #define CONFIG_NR_DRAM_BANKS            1               /* We have 1 bank of DRAM */
108 #define PHYS_SDRAM_1                    0xa0000000      /* SDRAM Bank #1 */
109 #define PHYS_SDRAM_1_SIZE               0x04000000      /* 64 MB */
110
111 #define CONFIG_SYS_DRAM_BASE            0xa0000000      /* CS0 */
112 #define CONFIG_SYS_DRAM_SIZE            0x04000000      /* 64 MB DRAM */
113
114 #define CONFIG_SYS_MEMTEST_START        0xa0400000      /* memtest works on */
115 #define CONFIG_SYS_MEMTEST_END          0xa0800000      /* 4 ... 8 MB in DRAM */
116
117 #define CONFIG_SYS_LOAD_ADDR            PHYS_SDRAM_1
118 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
119 #define CONFIG_SYS_INIT_SP_ADDR         0x5c010000
120
121 /*
122  * NOR FLASH
123  */
124 #ifdef  CONFIG_CMD_FLASH
125 #define PHYS_FLASH_1                    0x00000000      /* Flash Bank #1 */
126 #define PHYS_FLASH_SIZE                 0x02000000      /* 32 MB */
127 #define CONFIG_SYS_FLASH_BASE           PHYS_FLASH_1
128
129 #define CONFIG_SYS_FLASH_CFI
130 #define CONFIG_FLASH_CFI_DRIVER         1
131 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_32BIT
132
133 #define CONFIG_SYS_MAX_FLASH_SECT       (4 + 255)
134 #define CONFIG_SYS_MAX_FLASH_BANKS      1
135
136 #define CONFIG_SYS_FLASH_ERASE_TOUT     (25 * CONFIG_SYS_HZ)
137 #define CONFIG_SYS_FLASH_WRITE_TOUT     (25 * CONFIG_SYS_HZ)
138 #define CONFIG_SYS_FLASH_LOCK_TOUT      (25 * CONFIG_SYS_HZ)
139 #define CONFIG_SYS_FLASH_UNLOCK_TOUT    (25 * CONFIG_SYS_HZ)
140
141 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE       1
142 #define CONFIG_SYS_FLASH_PROTECTION             1
143
144 #define CONFIG_ENV_IS_IN_FLASH          1
145
146 #else   /* No flash */
147 #define CONFIG_SYS_NO_FLASH
148 #define CONFIG_ENV_IS_NOWHERE
149 #endif
150
151 #define CONFIG_SYS_MONITOR_BASE         0x0
152 #define CONFIG_SYS_MONITOR_LEN          0x40000
153
154 /* Skip factory configuration block */
155 #define CONFIG_ENV_ADDR                 \
156                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN + 0x40000)
157 #define CONFIG_ENV_SIZE                 0x40000
158 #define CONFIG_ENV_SECT_SIZE            0x40000
159
160 /*
161  * GPIO settings
162  */
163 #define CONFIG_SYS_GPSR0_VAL    0x00000000
164 #define CONFIG_SYS_GPSR1_VAL    0x00020000
165 #define CONFIG_SYS_GPSR2_VAL    0x0002c000
166 #define CONFIG_SYS_GPSR3_VAL    0x00000000
167
168 #define CONFIG_SYS_GPCR0_VAL    0x00000000
169 #define CONFIG_SYS_GPCR1_VAL    0x00000000
170 #define CONFIG_SYS_GPCR2_VAL    0x00000000
171 #define CONFIG_SYS_GPCR3_VAL    0x00000000
172
173 #define CONFIG_SYS_GPDR0_VAL    0xc8008000
174 #define CONFIG_SYS_GPDR1_VAL    0xfc02a981
175 #define CONFIG_SYS_GPDR2_VAL    0x92c3ffff
176 #define CONFIG_SYS_GPDR3_VAL    0x0061e804
177
178 #define CONFIG_SYS_GAFR0_L_VAL  0x80100000
179 #define CONFIG_SYS_GAFR0_U_VAL  0xa5c00010
180 #define CONFIG_SYS_GAFR1_L_VAL  0x6992901a
181 #define CONFIG_SYS_GAFR1_U_VAL  0xaaa50008
182 #define CONFIG_SYS_GAFR2_L_VAL  0xaaaaaaaa
183 #define CONFIG_SYS_GAFR2_U_VAL  0x4109a002
184 #define CONFIG_SYS_GAFR3_L_VAL  0x54000310
185 #define CONFIG_SYS_GAFR3_U_VAL  0x00005401
186
187 #define CONFIG_SYS_PSSR_VAL     0x30
188
189 /*
190  * Clock settings
191  */
192 #define CONFIG_SYS_CKEN         0x00500240
193 #define CONFIG_SYS_CCCR         0x02000290
194
195 /*
196  * Memory settings
197  */
198 #define CONFIG_SYS_MSC0_VAL     0x9ee1c5f2
199 #define CONFIG_SYS_MSC1_VAL     0x9ee1f994
200 #define CONFIG_SYS_MSC2_VAL     0x9ee19ee1
201 #define CONFIG_SYS_MDCNFG_VAL   0x090009c9
202 #define CONFIG_SYS_MDREFR_VAL   0x2003a031
203 #define CONFIG_SYS_MDMRS_VAL    0x00220022
204 #define CONFIG_SYS_FLYCNFG_VAL  0x00010001
205 #define CONFIG_SYS_SXCNFG_VAL   0x40044004
206
207 /*
208  * PCMCIA and CF Interfaces
209  */
210 #define CONFIG_SYS_MECR_VAL     0x00000000
211 #define CONFIG_SYS_MCMEM0_VAL   0x00028307
212 #define CONFIG_SYS_MCMEM1_VAL   0x00014307
213 #define CONFIG_SYS_MCATT0_VAL   0x00038787
214 #define CONFIG_SYS_MCATT1_VAL   0x0001c787
215 #define CONFIG_SYS_MCIO0_VAL    0x0002830f
216 #define CONFIG_SYS_MCIO1_VAL    0x0001430f
217
218 #include "pxa-common.h"
219
220 #endif /* __CONFIG_H */