2 * Toradex Colibri PXA270 configuration file
4 * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
5 * Copyright (C) 2015 Marcel Ziswiler <marcel@ziswiler.com>
7 * SPDX-License-Identifier: GPL-2.0+
14 * High Level Board Configuration Options
16 #define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */
17 #define CONFIG_SYS_GENERIC_BOARD
18 #define CONFIG_SYS_TEXT_BASE 0x0
21 * Environment settings
23 #define CONFIG_ENV_OVERWRITE
24 #define CONFIG_SYS_MALLOC_LEN (128 * 1024)
25 #define CONFIG_ARCH_CPU_INIT
26 #define CONFIG_BOOTCOMMAND \
27 "if mmc init && fatload mmc 0 0xa0000000 uImage; then " \
28 "bootm 0xa0000000; " \
30 "if usb reset && fatload usb 0 0xa0000000 uImage; then " \
31 "bootm 0xa0000000; " \
34 #define CONFIG_BOOTARGS "console=tty0 console=ttyS0,115200"
35 #define CONFIG_TIMESTAMP
36 #define CONFIG_BOOTDELAY 2 /* Autoboot delay */
37 #define CONFIG_CMDLINE_TAG
38 #define CONFIG_SETUP_MEMORY_TAGS
39 #define CONFIG_LZMA /* LZMA compression support */
40 #define CONFIG_OF_LIBFDT
43 * Serial Console Configuration
45 #define CONFIG_PXA_SERIAL
46 #define CONFIG_FFUART 1
47 #define CONFIG_CONS_INDEX 3
48 #define CONFIG_BAUDRATE 115200
51 * Bootloader Components Configuration
53 #include <config_cmd_default.h>
55 #undef CONFIG_CMD_LOADB /* Both together */
56 #undef CONFIG_CMD_LOADS /* saves 10 KB */
57 #define CONFIG_CMD_NET
58 #define CONFIG_CMD_ENV
59 #undef CONFIG_CMD_IMLS
60 #define CONFIG_CMD_MMC
61 #define CONFIG_CMD_USB
62 #define CONFIG_CMD_FLASH
65 * Networking Configuration
66 * chip on the Voipac PXA270 board
69 #define CONFIG_CMD_PING
70 #define CONFIG_CMD_DHCP
72 #define CONFIG_DRIVER_DM9000 1
73 #define CONFIG_DM9000_BASE 0x08000000
74 #define DM9000_IO (CONFIG_DM9000_BASE)
75 #define DM9000_DATA (CONFIG_DM9000_BASE + 4)
76 #define CONFIG_NET_RETRY_COUNT 10
78 #define CONFIG_BOOTP_BOOTFILESIZE
79 #define CONFIG_BOOTP_BOOTPATH
80 #define CONFIG_BOOTP_GATEWAY
81 #define CONFIG_BOOTP_HOSTNAME
85 * HUSH Shell Configuration
87 #define CONFIG_SYS_HUSH_PARSER 1
89 #undef CONFIG_SYS_LONGHELP /* Saves 10 KB */
90 #ifdef CONFIG_SYS_HUSH_PARSER
91 #define CONFIG_SYS_PROMPT "$ "
94 #define CONFIG_SYS_CBSIZE 256
95 #define CONFIG_SYS_PBSIZE \
96 (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
97 #define CONFIG_SYS_MAXARGS 16
98 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
99 #define CONFIG_SYS_DEVICE_NULLDEV 1
100 #define CONFIG_CMDLINE_EDITING 1
101 #define CONFIG_AUTO_COMPLETE 1
105 * Clock Configuration
107 #define CONFIG_SYS_CPUSPEED 0x290 /* 520MHz */
112 #define CONFIG_NR_DRAM_BANKS 1 /* We have 1 bank of DRAM */
113 #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
114 #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
116 #define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */
117 #define CONFIG_SYS_DRAM_SIZE 0x04000000 /* 64 MB DRAM */
119 #define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
120 #define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
122 #define CONFIG_SYS_LOAD_ADDR PHYS_SDRAM_1
123 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
124 #define CONFIG_SYS_INIT_SP_ADDR 0x5c010000
129 #ifdef CONFIG_CMD_FLASH
130 #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
131 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
133 #define CONFIG_SYS_FLASH_CFI
134 #define CONFIG_FLASH_CFI_DRIVER 1
136 #define CONFIG_SYS_MAX_FLASH_SECT (4 + 255)
137 #define CONFIG_SYS_MAX_FLASH_BANKS 1
139 #define CONFIG_SYS_FLASH_ERASE_TOUT (25 * CONFIG_SYS_HZ)
140 #define CONFIG_SYS_FLASH_WRITE_TOUT (25 * CONFIG_SYS_HZ)
142 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
143 #define CONFIG_SYS_FLASH_PROTECTION 1
145 #define CONFIG_ENV_IS_IN_FLASH 1
148 #define CONFIG_SYS_NO_FLASH
149 #define CONFIG_ENV_IS_NOWHERE
152 #define CONFIG_SYS_MONITOR_BASE 0x0
153 #define CONFIG_SYS_MONITOR_LEN 0x80000
155 #define CONFIG_ENV_ADDR \
156 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
157 #define CONFIG_ENV_SIZE 0x40000
158 #define CONFIG_ENV_SECT_SIZE 0x40000
159 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
160 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
165 #define CONFIG_SYS_GPSR0_VAL 0x00000000
166 #define CONFIG_SYS_GPSR1_VAL 0x00020000
167 #define CONFIG_SYS_GPSR2_VAL 0x0002C000
168 #define CONFIG_SYS_GPSR3_VAL 0x00000000
170 #define CONFIG_SYS_GPCR0_VAL 0x00000000
171 #define CONFIG_SYS_GPCR1_VAL 0x00000000
172 #define CONFIG_SYS_GPCR2_VAL 0x00000000
173 #define CONFIG_SYS_GPCR3_VAL 0x00000000
175 #define CONFIG_SYS_GPDR0_VAL 0x08000000
176 #define CONFIG_SYS_GPDR1_VAL 0x0002A981
177 #define CONFIG_SYS_GPDR2_VAL 0x0202FC00
178 #define CONFIG_SYS_GPDR3_VAL 0x00000000
180 #define CONFIG_SYS_GAFR0_L_VAL 0x00100000
181 #define CONFIG_SYS_GAFR0_U_VAL 0x00C00010
182 #define CONFIG_SYS_GAFR1_L_VAL 0x999A901A
183 #define CONFIG_SYS_GAFR1_U_VAL 0xAAA00008
184 #define CONFIG_SYS_GAFR2_L_VAL 0xAAAAAAAA
185 #define CONFIG_SYS_GAFR2_U_VAL 0x0109A000
186 #define CONFIG_SYS_GAFR3_L_VAL 0x54000300
187 #define CONFIG_SYS_GAFR3_U_VAL 0x00024001
189 #define CONFIG_SYS_PSSR_VAL 0x30
194 #define CONFIG_SYS_CKEN 0x00500240
195 #define CONFIG_SYS_CCCR 0x02000290
200 #define CONFIG_SYS_MSC0_VAL 0x000095f2
201 #define CONFIG_SYS_MSC1_VAL 0x00007ff4
202 #define CONFIG_SYS_MSC2_VAL 0x00000000
203 #define CONFIG_SYS_MDCNFG_VAL 0x08000ac9
204 #define CONFIG_SYS_MDREFR_VAL 0x2013e01e
205 #define CONFIG_SYS_MDMRS_VAL 0x00320032
206 #define CONFIG_SYS_FLYCNFG_VAL 0x00000000
207 #define CONFIG_SYS_SXCNFG_VAL 0x40044004
210 * PCMCIA and CF Interfaces
212 #define CONFIG_SYS_MECR_VAL 0x00000001
213 #define CONFIG_SYS_MCMEM0_VAL 0x00014307
214 #define CONFIG_SYS_MCMEM1_VAL 0x00014307
215 #define CONFIG_SYS_MCATT0_VAL 0x0001c787
216 #define CONFIG_SYS_MCATT1_VAL 0x0001c787
217 #define CONFIG_SYS_MCIO0_VAL 0x0001430f
218 #define CONFIG_SYS_MCIO1_VAL 0x0001430f
220 #include "pxa-common.h"
222 #endif /* __CONFIG_H */