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Convert CONFIG_VGA_AS_SINGLE_DEVICE to Kconfig
[u-boot] / include / configs / controlcenterd.h
1 /*
2  * (C) Copyright 2013
3  * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
4  *
5  * based on P1022DS.h
6  *
7  * See file CREDITS for list of people who contributed to this
8  * project.
9  *
10  * This program is free software; you can redistribute it and/or
11  * modify it under the terms of the GNU General Public License as
12  * published by the Free Software Foundation; either version 2 of
13  * the License, or (at your option) any later version.
14  *
15  * This program is distributed in the hope that it will be useful,
16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18  * GNU General Public License for more details.
19  *
20  * You should have received a copy of the GNU General Public License
21  * along with this program; if not, write to the Free Software
22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23  * MA 02111-1307 USA
24  */
25
26 #ifndef __CONFIG_H
27 #define __CONFIG_H
28
29 #ifdef CONFIG_SDCARD
30 #define CONFIG_RAMBOOT_SDCARD
31 #endif
32
33 #ifdef CONFIG_SPIFLASH
34 #define CONFIG_RAMBOOT_SPIFLASH
35 #endif
36
37 /* High Level Configuration Options */
38 #define CONFIG_BOOKE                    /* BOOKE */
39 #define CONFIG_E500                     /* BOOKE e500 family */
40 #define CONFIG_P1022
41 #define CONFIG_CONTROLCENTERD
42 #define CONFIG_MP                       /* support multiple processors */
43
44 #define CONFIG_SYS_NO_FLASH
45 #define CONFIG_ENABLE_36BIT_PHYS
46 #define CONFIG_FSL_LAW                  /* Use common FSL init code */
47
48 #ifdef CONFIG_PHYS_64BIT
49 #define CONFIG_ADDR_MAP
50 #define CONFIG_SYS_NUM_ADDR_MAP         16      /* number of TLB1 entries */
51 #endif
52
53 #define CONFIG_L2_CACHE
54 #define CONFIG_BTB
55
56 #define CONFIG_SYS_CLK_FREQ     66666600
57 #define CONFIG_DDR_CLK_FREQ     66666600
58
59 #define CONFIG_SYS_RAMBOOT
60
61 #ifdef CONFIG_TRAILBLAZER
62
63 #define CONFIG_SYS_TEXT_BASE            0xf8fc0000
64 #define CONFIG_RESET_VECTOR_ADDRESS     0xf8fffffc
65 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024)
66
67 /*
68  * Config the L2 Cache
69  */
70 #define CONFIG_SYS_INIT_L2_ADDR         0xf8fc0000
71 #ifdef CONFIG_PHYS_64BIT
72 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    0xff8fc0000ull
73 #else
74 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
75 #endif
76 #define CONFIG_SYS_L2_SIZE              (256 << 10)
77 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
78
79 #else /* CONFIG_TRAILBLAZER */
80
81 #define CONFIG_SYS_TEXT_BASE            0x11000000
82 #define CONFIG_RESET_VECTOR_ADDRESS     0x1107fffc
83 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)
84
85 #endif /* CONFIG_TRAILBLAZER */
86
87 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
88 #define CONFIG_SYS_MALLOC_LEN           (10 * 1024 * 1024)
89
90 /*
91  * Memory map
92  *
93  * 0x0000_0000  0x3fff_ffff     DDR                     1G Cacheable
94  * 0xc000_0000  0xdfff_ffff     PCI Express Mem         512M non-cacheable
95  * 0xffc0_0000  0xffc2_ffff     PCI IO range            192K non-cacheable
96  *
97  * Localbus non-cacheable
98  * 0xe000_0000  0xe00f_ffff     eLBC                    1M non-cacheable
99  * 0xf8fc0000   0xf8ff_ffff     L2 SRAM                 256k Cacheable
100  * 0xffd0_0000  0xffd0_3fff     L1 for stack            16K Cacheable TLB0
101  * 0xffe0_0000  0xffef_ffff     CCSR                    1M non-cacheable
102  */
103
104 #define CONFIG_SYS_INIT_RAM_LOCK
105 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000 /* Initial L1 address */
106 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000 /* used area in RAM */
107 #define CONFIG_SYS_GBL_DATA_OFFSET      \
108         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
109 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
110
111 #ifdef CONFIG_TRAILBLAZER
112 /* leave CCSRBAR at default, because u-boot expects it to be exactly there */
113 #define CONFIG_SYS_CCSRBAR              CONFIG_SYS_CCSRBAR_DEFAULT
114 #else
115 #define CONFIG_SYS_CCSRBAR              0xffe00000
116 #endif
117 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
118 #define CONFIG_SYS_MPC85xx_GPIO3_ADDR   (CONFIG_SYS_CCSRBAR+0xf200)
119
120 /*
121  * DDR Setup
122  */
123
124 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
125 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
126 #define CONFIG_SYS_SDRAM_SIZE 1024
127 #define CONFIG_VERY_BIG_RAM
128
129 #define CONFIG_SYS_FSL_DDR3
130 #define CONFIG_NUM_DDR_CONTROLLERS      1
131 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
132 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
133
134 #define CONFIG_SYS_MEMTEST_START        0x00000000
135 #define CONFIG_SYS_MEMTEST_END          0x3fffffff
136
137 #ifdef CONFIG_TRAILBLAZER
138 #define CONFIG_SPD_EEPROM
139 #define SPD_EEPROM_ADDRESS 0x52
140 /*#define CONFIG_FSL_DDR_INTERACTIVE*/
141 #endif
142
143 /*
144  * Local Bus Definitions
145  */
146 #define CONFIG_FSL_ELBC                 /* Has Enhanced localbus controller */
147
148 #define CONFIG_SYS_ELBC_BASE            0xe0000000
149 #ifdef CONFIG_PHYS_64BIT
150 #define CONFIG_SYS_ELBC_BASE_PHYS       0xfe0000000ull
151 #else
152 #define CONFIG_SYS_ELBC_BASE_PHYS       CONFIG_SYS_ELBC_BASE
153 #endif
154
155 #define CONFIG_UART_BR_PRELIM  \
156         (BR_PHYS_ADDR((CONFIG_SYS_ELBC_BASE_PHYS)) | BR_PS_8 | BR_V)
157 #define CONFIG_UART_OR_PRELIM   (OR_AM_32KB | 0xff7)
158
159 #define CONFIG_SYS_BR0_PRELIM   0 /* CS0 was originally intended for FPGA */
160 #define CONFIG_SYS_OR0_PRELIM   0 /* debugging, was never used */
161
162 #define CONFIG_SYS_BR1_PRELIM   CONFIG_UART_BR_PRELIM
163 #define CONFIG_SYS_OR1_PRELIM   CONFIG_UART_OR_PRELIM
164
165 /*
166  * Serial Port
167  */
168 #define CONFIG_CONS_INDEX               2
169 #define CONFIG_SYS_NS16550_SERIAL
170 #define CONFIG_SYS_NS16550_REG_SIZE     1
171 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
172
173 #define CONFIG_SYS_BAUDRATE_TABLE       \
174         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
175
176 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
177 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
178
179 /*
180  * I2C
181  */
182 #define CONFIG_SYS_I2C
183 #define CONFIG_SYS_I2C_FSL
184 #define CONFIG_SYS_FSL_I2C_SPEED        400000
185 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
186 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
187 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
188 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
189 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
190
191 #ifndef CONFIG_TRAILBLAZER
192 #endif
193
194 #define CONFIG_PCA9698                  /* NXP PCA9698 */
195
196 #define CONFIG_CMD_EEPROM
197 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
198 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
199
200 #ifndef CONFIG_TRAILBLAZER
201 /*
202  * eSPI - Enhanced SPI
203  */
204 #define CONFIG_HARD_SPI
205
206 #define CONFIG_SF_DEFAULT_SPEED         10000000
207 #define CONFIG_SF_DEFAULT_MODE          0
208 #endif
209
210 #define CONFIG_SHA1
211
212 /*
213  * MMC
214  */
215 #define CONFIG_MMC
216 #define CONFIG_GENERIC_MMC
217
218 #define CONFIG_FSL_ESDHC
219 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
220
221 #ifndef CONFIG_TRAILBLAZER
222
223 /*
224  * Video
225  */
226 #define CONFIG_FSL_DIU_FB
227 #define CONFIG_SYS_DIU_ADDR     (CONFIG_SYS_CCSRBAR + 0x10000)
228 #define CONFIG_CMD_BMP
229
230 /*
231  * General PCI
232  * Memory space is mapped 1-1, but I/O space must start from 0.
233  */
234 #define CONFIG_PCI                      /* Enable PCI/PCIE */
235 #define CONFIG_PCIE1                    /* PCIE controller 1 (slot 1) */
236 #define CONFIG_PCI_INDIRECT_BRIDGE
237 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
238 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
239 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
240 #define CONFIG_CMD_PCI
241
242 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
243 #define CONFIG_FSL_PCIE_RESET           /* need PCIe reset errata */
244
245 #define CONFIG_SYS_PCIE1_MEM_VIRT       0xc0000000
246 #ifdef CONFIG_PHYS_64BIT
247 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
248 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc40000000ull
249 #else
250 #define CONFIG_SYS_PCIE1_MEM_BUS        0xc0000000
251 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc0000000
252 #endif
253 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
254 #define CONFIG_SYS_PCIE1_IO_VIRT        0xffc20000
255 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
256 #ifdef CONFIG_PHYS_64BIT
257 #define CONFIG_SYS_PCIE1_IO_PHYS        0xfffc20000ull
258 #else
259 #define CONFIG_SYS_PCIE1_IO_PHYS        0xffc20000
260 #endif
261 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
262
263 /*
264  * SATA
265  */
266 #define CONFIG_LIBATA
267 #define CONFIG_LBA48
268 #define CONFIG_CMD_SATA
269
270 #define CONFIG_FSL_SATA
271 #define CONFIG_SYS_SATA_MAX_DEVICE      2
272 #define CONFIG_SATA1
273 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
274 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
275 #define CONFIG_SATA2
276 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
277 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
278
279 /*
280  * Ethernet
281  */
282 #define CONFIG_TSEC_ENET
283
284 #define CONFIG_TSECV2
285
286 #define CONFIG_MII                      /* MII PHY management */
287 #define CONFIG_TSEC1            1
288 #define CONFIG_TSEC1_NAME       "eTSEC1"
289 #define CONFIG_TSEC2            1
290 #define CONFIG_TSEC2_NAME       "eTSEC2"
291
292 #define TSEC1_PHY_ADDR          0
293 #define TSEC2_PHY_ADDR          1
294
295 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
296 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
297
298 #define TSEC1_PHYIDX            0
299 #define TSEC2_PHYIDX            0
300
301 #define CONFIG_ETHPRIME         "eTSEC1"
302
303 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
304
305 /*
306  * USB
307  */
308 #define CONFIG_USB_EHCI
309
310 #define CONFIG_HAS_FSL_DR_USB
311 #define CONFIG_USB_EHCI_FSL
312 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
313
314 #endif /* CONFIG_TRAILBLAZER */
315
316 /*
317  * Environment
318  */
319 #if defined(CONFIG_TRAILBLAZER)
320 #define CONFIG_ENV_IS_NOWHERE
321 #define CONFIG_ENV_SIZE         0x2000          /* 8KB */
322 #elif defined(CONFIG_RAMBOOT_SPIFLASH)
323 #define CONFIG_ENV_IS_IN_SPI_FLASH
324 #define CONFIG_ENV_SPI_BUS      0
325 #define CONFIG_ENV_SPI_CS       0
326 #define CONFIG_ENV_SPI_MAX_HZ   10000000
327 #define CONFIG_ENV_SPI_MODE     0
328 #define CONFIG_ENV_SIZE         0x2000          /* 8KB */
329 #define CONFIG_ENV_OFFSET       0x100000        /* 1MB */
330 #define CONFIG_ENV_SECT_SIZE    0x10000
331 #elif defined(CONFIG_RAMBOOT_SDCARD)
332 #define CONFIG_ENV_IS_IN_MMC
333 #define CONFIG_FSL_FIXED_MMC_LOCATION
334 #define CONFIG_ENV_SIZE         0x2000
335 #define CONFIG_SYS_MMC_ENV_DEV  0
336 #endif
337
338 #define CONFIG_SYS_EXTRA_ENV_RELOC
339
340 /*
341  * Command line configuration.
342  */
343 #ifndef CONFIG_TRAILBLAZER
344 #define CONFIG_SYS_LONGHELP
345 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
346 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
347 #endif /* CONFIG_TRAILBLAZER */
348
349 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
350 #ifdef CONFIG_CMD_KGDB
351 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
352 #else
353 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
354 #endif
355 /* Print Buffer Size */
356 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
357 #define CONFIG_SYS_MAXARGS      16
358 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
359
360 #ifndef CONFIG_TRAILBLAZER
361
362 #define CONFIG_CMD_ERRATA
363 #define CONFIG_CMD_IRQ
364 #define CONFIG_CMD_REGINFO
365
366 /*
367  * Board initialisation callbacks
368  */
369 #define CONFIG_BOARD_EARLY_INIT_F
370 #define CONFIG_BOARD_EARLY_INIT_R
371 #define CONFIG_MISC_INIT_R
372 #define CONFIG_LAST_STAGE_INIT
373
374 #else /* CONFIG_TRAILBLAZER */
375
376 #define CONFIG_BOARD_EARLY_INIT_F
377 #define CONFIG_BOARD_EARLY_INIT_R
378 #define CONFIG_LAST_STAGE_INIT
379
380 #endif /* CONFIG_TRAILBLAZER */
381
382 /*
383  * Miscellaneous configurable options
384  */
385 #define CONFIG_HW_WATCHDOG
386 #define CONFIG_LOADS_ECHO
387 #define CONFIG_SYS_LOADS_BAUD_CHANGE
388 #define CONFIG_DOS_PARTITION
389
390 /*
391  * For booting Linux, the board info and command line data
392  * have to be in the first 64 MB of memory, since this is
393  * the maximum mapped by the Linux kernel during initialization.
394  */
395 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Linux Memory map */
396 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
397
398 /*
399  * Environment Configuration
400  */
401
402 #ifdef CONFIG_TRAILBLAZER
403
404 #define CONFIG_BAUDRATE 115200
405
406 #define CONFIG_EXTRA_ENV_SETTINGS                               \
407         "mp_holdoff=1\0"
408
409 #else
410
411 #define CONFIG_HOSTNAME         controlcenterd
412 #define CONFIG_ROOTPATH         "/opt/nfsroot"
413 #define CONFIG_BOOTFILE         "uImage"
414 #define CONFIG_UBOOTPATH        u-boot.bin      /* U-Boot image on TFTP */
415
416 #define CONFIG_LOADADDR         1000000
417
418
419 #define CONFIG_BAUDRATE 115200
420
421 #define CONFIG_EXTRA_ENV_SETTINGS                               \
422         "netdev=eth0\0"                                         \
423         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
424         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
425         "tftpflash=tftpboot $loadaddr $uboot && "               \
426                 "protect off $ubootaddr +$filesize && "         \
427                 "erase $ubootaddr +$filesize && "               \
428                 "cp.b $loadaddr $ubootaddr $filesize && "       \
429                 "protect on $ubootaddr +$filesize && "          \
430                 "cmp.b $loadaddr $ubootaddr $filesize\0"        \
431         "consoledev=ttyS1\0"                                    \
432         "ramdiskaddr=2000000\0"                                 \
433         "ramdiskfile=rootfs.ext2.gz.uboot\0"                    \
434         "fdtaddr=1e00000\0"                                     \
435         "fdtfile=controlcenterd.dtb\0"                          \
436         "bdev=sda3\0"
437
438 /* these are used and NUL-terminated in env_default.h */
439 #define CONFIG_NFSBOOTCOMMAND                                           \
440         "setenv bootargs root=/dev/nfs rw "                             \
441         "nfsroot=$serverip:$rootpath "                                  \
442         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
443         "console=$consoledev,$baudrate $othbootargs $videobootargs;"    \
444         "tftp $loadaddr $bootfile;"                                     \
445         "tftp $fdtaddr $fdtfile;"                                       \
446         "bootm $loadaddr - $fdtaddr"
447
448 #define CONFIG_RAMBOOTCOMMAND                                           \
449         "setenv bootargs root=/dev/ram rw "                             \
450         "console=$consoledev,$baudrate $othbootargs $videobootargs;"    \
451         "tftp $ramdiskaddr $ramdiskfile;"                               \
452         "tftp $loadaddr $bootfile;"                                     \
453         "tftp $fdtaddr $fdtfile;"                                       \
454         "bootm $loadaddr $ramdiskaddr $fdtaddr"
455
456 #define CONFIG_BOOTCOMMAND              CONFIG_RAMBOOTCOMMAND
457
458 #endif /* CONFIG_TRAILBLAZER */
459
460 #endif