3 * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #define CONFIG_PHYS_64BIT
34 #define CONFIG_RAMBOOT_SDCARD
37 #ifdef CONFIG_SPIFLASH
38 #define CONFIG_RAMBOOT_SPIFLASH
41 /* High Level Configuration Options */
42 #define CONFIG_BOOKE /* BOOKE */
43 #define CONFIG_E500 /* BOOKE e500 family */
45 #define CONFIG_CONTROLCENTERD
46 #define CONFIG_MP /* support multiple processors */
49 #define CONFIG_SYS_NO_FLASH
50 #define CONFIG_ENABLE_36BIT_PHYS
51 #define CONFIG_FSL_LAW /* Use common FSL init code */
53 #ifdef CONFIG_TRAILBLAZER
54 #define CONFIG_IDENT_STRING " controlcenterd trailblazer 0.01"
56 #define CONFIG_IDENT_STRING " controlcenterd 0.01"
59 #ifdef CONFIG_PHYS_64BIT
60 #define CONFIG_ADDR_MAP
61 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
64 #define CONFIG_L2_CACHE
67 #define CONFIG_SYS_CLK_FREQ 66666600
68 #define CONFIG_DDR_CLK_FREQ 66666600
70 #define CONFIG_SYS_RAMBOOT
72 #ifdef CONFIG_TRAILBLAZER
74 #define CONFIG_SYS_TEXT_BASE 0xf8fc0000
75 #define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc
76 #define CONFIG_SYS_MONITOR_LEN (256 * 1024)
81 #define CONFIG_SYS_INIT_L2_ADDR 0xf8fc0000
82 #ifdef CONFIG_PHYS_64BIT
83 #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8fc0000ull
85 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
87 #define CONFIG_SYS_L2_SIZE (256 << 10)
88 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
90 #else /* CONFIG_TRAILBLAZER */
92 #define CONFIG_SYS_TEXT_BASE 0x11000000
93 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
94 #define CONFIG_SYS_MONITOR_LEN (512 * 1024)
96 #endif /* CONFIG_TRAILBLAZER */
98 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
99 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
105 * 0x0000_0000 0x3fff_ffff DDR 1G Cacheable
106 * 0xc000_0000 0xdfff_ffff PCI Express Mem 512M non-cacheable
107 * 0xffc0_0000 0xffc2_ffff PCI IO range 192K non-cacheable
109 * Localbus non-cacheable
110 * 0xe000_0000 0xe00f_ffff eLBC 1M non-cacheable
111 * 0xf8fc0000 0xf8ff_ffff L2 SRAM 256k Cacheable
112 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
113 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
116 #define CONFIG_SYS_INIT_RAM_LOCK
117 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
118 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* used area in RAM */
119 #define CONFIG_SYS_GBL_DATA_OFFSET \
120 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
121 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
123 #ifdef CONFIG_TRAILBLAZER
124 /* leave CCSRBAR at default, because u-boot expects it to be exactly there */
125 #define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT
127 #define CONFIG_SYS_CCSRBAR 0xffe00000
129 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
130 #define CONFIG_SYS_MPC85xx_GPIO3_ADDR (CONFIG_SYS_CCSRBAR+0xf200)
136 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
137 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
138 #define CONFIG_SYS_SDRAM_SIZE 1024
139 #define CONFIG_VERY_BIG_RAM
141 #define CONFIG_SYS_FSL_DDR3
142 #define CONFIG_NUM_DDR_CONTROLLERS 1
143 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
144 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
146 #define CONFIG_SYS_MEMTEST_START 0x00000000
147 #define CONFIG_SYS_MEMTEST_END 0x3fffffff
149 #ifdef CONFIG_TRAILBLAZER
150 #define CONFIG_SPD_EEPROM
151 #define SPD_EEPROM_ADDRESS 0x52
152 /*#define CONFIG_FSL_DDR_INTERACTIVE*/
156 * Local Bus Definitions
158 #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
160 #define CONFIG_SYS_ELBC_BASE 0xe0000000
161 #ifdef CONFIG_PHYS_64BIT
162 #define CONFIG_SYS_ELBC_BASE_PHYS 0xfe0000000ull
164 #define CONFIG_SYS_ELBC_BASE_PHYS CONFIG_SYS_ELBC_BASE
167 #define CONFIG_UART_BR_PRELIM \
168 (BR_PHYS_ADDR((CONFIG_SYS_ELBC_BASE_PHYS)) | BR_PS_8 | BR_V)
169 #define CONFIG_UART_OR_PRELIM (OR_AM_32KB | 0xff7)
171 #define CONFIG_SYS_BR0_PRELIM 0 /* CS0 was originally intended for FPGA */
172 #define CONFIG_SYS_OR0_PRELIM 0 /* debugging, was never used */
174 #define CONFIG_SYS_BR1_PRELIM CONFIG_UART_BR_PRELIM
175 #define CONFIG_SYS_OR1_PRELIM CONFIG_UART_OR_PRELIM
180 #define CONFIG_CONS_INDEX 2
181 #define CONFIG_SYS_NS16550_SERIAL
182 #define CONFIG_SYS_NS16550_REG_SIZE 1
183 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
185 #define CONFIG_SYS_BAUDRATE_TABLE \
186 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
188 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
189 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
194 #define CONFIG_SYS_I2C
195 #define CONFIG_SYS_I2C_FSL
196 #define CONFIG_SYS_FSL_I2C_SPEED 400000
197 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
198 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
199 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
200 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
201 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
203 #ifndef CONFIG_TRAILBLAZER
204 #define CONFIG_CMD_I2C
207 #define CONFIG_PCA9698 /* NXP PCA9698 */
209 #define CONFIG_CMD_EEPROM
210 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
211 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
213 #ifndef CONFIG_TRAILBLAZER
215 * eSPI - Enhanced SPI
217 #define CONFIG_HARD_SPI
220 #define CONFIG_CMD_SF
221 #define CONFIG_SF_DEFAULT_SPEED 10000000
222 #define CONFIG_SF_DEFAULT_MODE 0
231 #define CONFIG_GENERIC_MMC
232 #define CONFIG_CMD_MMC
234 #define CONFIG_FSL_ESDHC
235 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
238 #ifndef CONFIG_TRAILBLAZER
243 #define CONFIG_FSL_DIU_FB
244 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000)
246 #define CONFIG_CFB_CONSOLE
247 #define CONFIG_VGA_AS_SINGLE_DEVICE
248 #define CONFIG_CMD_BMP
252 * Memory space is mapped 1-1, but I/O space must start from 0.
254 #define CONFIG_PCI /* Enable PCI/PCIE */
255 #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
256 #define CONFIG_PCI_INDIRECT_BRIDGE
257 #define CONFIG_PCI_PNP /* do pci plug-and-play */
258 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
259 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
260 #define CONFIG_CMD_PCI
262 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
263 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
265 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
266 #ifdef CONFIG_PHYS_64BIT
267 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
268 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
270 #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
271 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
273 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
274 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
275 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
276 #ifdef CONFIG_PHYS_64BIT
277 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull
279 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
281 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
286 #define CONFIG_LIBATA
288 #define CONFIG_CMD_SATA
290 #define CONFIG_FSL_SATA
291 #define CONFIG_SYS_SATA_MAX_DEVICE 2
293 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
294 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
296 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
297 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
302 #define CONFIG_TSEC_ENET
304 #define CONFIG_TSECV2
306 #define CONFIG_MII /* MII PHY management */
307 #define CONFIG_TSEC1 1
308 #define CONFIG_TSEC1_NAME "eTSEC1"
309 #define CONFIG_TSEC2 1
310 #define CONFIG_TSEC2_NAME "eTSEC2"
312 #define TSEC1_PHY_ADDR 0
313 #define TSEC2_PHY_ADDR 1
315 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
316 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
318 #define TSEC1_PHYIDX 0
319 #define TSEC2_PHYIDX 0
321 #define CONFIG_ETHPRIME "eTSEC1"
323 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
328 #define CONFIG_USB_EHCI
329 #define CONFIG_CMD_USB
330 #define CONFIG_USB_STORAGE
332 #define CONFIG_HAS_FSL_DR_USB
333 #define CONFIG_USB_EHCI_FSL
334 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
336 #endif /* CONFIG_TRAILBLAZER */
341 #if defined(CONFIG_TRAILBLAZER)
342 #define CONFIG_ENV_IS_NOWHERE
343 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
344 #elif defined(CONFIG_RAMBOOT_SPIFLASH)
345 #define CONFIG_ENV_IS_IN_SPI_FLASH
346 #define CONFIG_ENV_SPI_BUS 0
347 #define CONFIG_ENV_SPI_CS 0
348 #define CONFIG_ENV_SPI_MAX_HZ 10000000
349 #define CONFIG_ENV_SPI_MODE 0
350 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
351 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
352 #define CONFIG_ENV_SECT_SIZE 0x10000
353 #elif defined(CONFIG_RAMBOOT_SDCARD)
354 #define CONFIG_ENV_IS_IN_MMC
355 #define CONFIG_FSL_FIXED_MMC_LOCATION
356 #define CONFIG_ENV_SIZE 0x2000
357 #define CONFIG_SYS_MMC_ENV_DEV 0
360 #define CONFIG_SYS_EXTRA_ENV_RELOC
362 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
365 * Command line configuration.
367 #ifndef CONFIG_TRAILBLAZER
368 #define CONFIG_SYS_LONGHELP
369 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
370 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
371 #endif /* CONFIG_TRAILBLAZER */
373 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
374 #ifdef CONFIG_CMD_KGDB
375 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
377 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
379 /* Print Buffer Size */
380 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
381 #define CONFIG_SYS_MAXARGS 16
382 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
384 #ifndef CONFIG_TRAILBLAZER
386 #define CONFIG_CMD_ERRATA
387 #define CONFIG_CMD_EXT2
388 #define CONFIG_CMD_FAT
389 #define CONFIG_CMD_IRQ
390 #define CONFIG_CMD_MII
391 #define CONFIG_CMD_PING
392 #define CONFIG_CMD_REGINFO
395 * Board initialisation callbacks
397 #define CONFIG_BOARD_EARLY_INIT_F
398 #define CONFIG_BOARD_EARLY_INIT_R
399 #define CONFIG_MISC_INIT_R
400 #define CONFIG_LAST_STAGE_INIT
402 #else /* CONFIG_TRAILBLAZER */
404 #define CONFIG_BOARD_EARLY_INIT_F
405 #define CONFIG_BOARD_EARLY_INIT_R
406 #define CONFIG_LAST_STAGE_INIT
408 #endif /* CONFIG_TRAILBLAZER */
411 * Miscellaneous configurable options
413 #define CONFIG_HW_WATCHDOG
414 #define CONFIG_LOADS_ECHO
415 #define CONFIG_SYS_LOADS_BAUD_CHANGE
416 #define CONFIG_DOS_PARTITION
419 * For booting Linux, the board info and command line data
420 * have to be in the first 64 MB of memory, since this is
421 * the maximum mapped by the Linux kernel during initialization.
423 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Linux Memory map */
424 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
427 * Environment Configuration
430 #ifdef CONFIG_TRAILBLAZER
432 #define CONFIG_BOOTDELAY 0 /* -1 disables auto-boot */
433 #define CONFIG_BAUDRATE 115200
435 #define CONFIG_EXTRA_ENV_SETTINGS \
440 #define CONFIG_HOSTNAME controlcenterd
441 #define CONFIG_ROOTPATH "/opt/nfsroot"
442 #define CONFIG_BOOTFILE "uImage"
443 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP */
445 #define CONFIG_LOADADDR 1000000
447 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
449 #define CONFIG_BAUDRATE 115200
451 #define CONFIG_EXTRA_ENV_SETTINGS \
453 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
454 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
455 "tftpflash=tftpboot $loadaddr $uboot && " \
456 "protect off $ubootaddr +$filesize && " \
457 "erase $ubootaddr +$filesize && " \
458 "cp.b $loadaddr $ubootaddr $filesize && " \
459 "protect on $ubootaddr +$filesize && " \
460 "cmp.b $loadaddr $ubootaddr $filesize\0" \
461 "consoledev=ttyS1\0" \
462 "ramdiskaddr=2000000\0" \
463 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
465 "fdtfile=controlcenterd.dtb\0" \
468 /* these are used and NUL-terminated in env_default.h */
469 #define CONFIG_NFSBOOTCOMMAND \
470 "setenv bootargs root=/dev/nfs rw " \
471 "nfsroot=$serverip:$rootpath " \
472 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
473 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \
474 "tftp $loadaddr $bootfile;" \
475 "tftp $fdtaddr $fdtfile;" \
476 "bootm $loadaddr - $fdtaddr"
478 #define CONFIG_RAMBOOTCOMMAND \
479 "setenv bootargs root=/dev/ram rw " \
480 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \
481 "tftp $ramdiskaddr $ramdiskfile;" \
482 "tftp $loadaddr $bootfile;" \
483 "tftp $fdtaddr $fdtfile;" \
484 "bootm $loadaddr $ramdiskaddr $fdtaddr"
486 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
488 #endif /* CONFIG_TRAILBLAZER */