2 * Copyright 2009-2011 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * Corenet DS style board configuration file
29 #include "../board/freescale/common/ics307_clk.h"
31 #ifdef CONFIG_RAMBOOT_PBL
32 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
33 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
36 /* High Level Configuration Options */
38 #define CONFIG_E500 /* BOOKE e500 family */
39 #define CONFIG_E500MC /* BOOKE e500mc family */
40 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
41 #define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */
42 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
43 #define CONFIG_MP /* support multiple processors */
45 #ifndef CONFIG_SYS_TEXT_BASE
46 #define CONFIG_SYS_TEXT_BASE 0xeff80000
49 #ifndef CONFIG_RESET_VECTOR_ADDRESS
50 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
53 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
54 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
55 #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
56 #define CONFIG_PCI /* Enable PCI/PCIE */
57 #define CONFIG_PCIE1 /* PCIE controler 1 */
58 #define CONFIG_PCIE2 /* PCIE controler 2 */
59 #define CONFIG_PCIE3 /* PCIE controler 3 */
60 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
61 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
63 #define CONFIG_SYS_SRIO
64 #define CONFIG_SRIO1 /* SRIO port 1 */
65 #define CONFIG_SRIO2 /* SRIO port 2 */
67 #define CONFIG_FSL_LAW /* Use common FSL init code */
69 #define CONFIG_ENV_OVERWRITE
71 #ifdef CONFIG_SYS_NO_FLASH
72 #define CONFIG_ENV_IS_NOWHERE
74 #define CONFIG_FLASH_CFI_DRIVER
75 #define CONFIG_SYS_FLASH_CFI
78 #if defined(CONFIG_SPIFLASH)
79 #define CONFIG_SYS_EXTRA_ENV_RELOC
80 #define CONFIG_ENV_IS_IN_SPI_FLASH
81 #define CONFIG_ENV_SPI_BUS 0
82 #define CONFIG_ENV_SPI_CS 0
83 #define CONFIG_ENV_SPI_MAX_HZ 10000000
84 #define CONFIG_ENV_SPI_MODE 0
85 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
86 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
87 #define CONFIG_ENV_SECT_SIZE 0x10000
88 #elif defined(CONFIG_SDCARD)
89 #define CONFIG_SYS_EXTRA_ENV_RELOC
90 #define CONFIG_ENV_IS_IN_MMC
91 #define CONFIG_SYS_MMC_ENV_DEV 0
92 #define CONFIG_ENV_SIZE 0x2000
93 #define CONFIG_ENV_OFFSET (512 * 1097)
95 #define CONFIG_ENV_IS_IN_FLASH
96 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
97 #define CONFIG_ENV_SIZE 0x2000
98 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
101 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
104 * These can be toggled for performance analysis, otherwise use default.
106 #define CONFIG_SYS_CACHE_STASHING
107 #define CONFIG_BACKSIDE_L2_CACHE
108 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
109 #define CONFIG_BTB /* toggle branch predition */
110 #define CONFIG_DDR_ECC
111 #ifdef CONFIG_DDR_ECC
112 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
113 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
116 #define CONFIG_ENABLE_36BIT_PHYS
118 #ifdef CONFIG_PHYS_64BIT
119 #define CONFIG_ADDR_MAP
120 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
123 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
124 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
125 #define CONFIG_SYS_MEMTEST_END 0x00400000
126 #define CONFIG_SYS_ALT_MEMTEST
127 #define CONFIG_PANIC_HANG /* do not reset board on panic */
130 * Config the L3 Cache as L3 SRAM
132 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
133 #ifdef CONFIG_PHYS_64BIT
134 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE)
136 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR
138 #define CONFIG_SYS_L3_SIZE (1024 << 10)
139 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
142 * Base addresses -- Note these are effective addresses where the
143 * actual resources get mapped (not physical addresses)
145 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 /* CCSRBAR Default */
146 #define CONFIG_SYS_CCSRBAR 0xfe000000 /* relocated CCSRBAR */
147 #ifdef CONFIG_PHYS_64BIT
148 #define CONFIG_SYS_CCSRBAR_PHYS 0xffe000000ull /* physical addr of CCSRBAR */
150 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
152 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
154 #ifdef CONFIG_PHYS_64BIT
155 #define CONFIG_SYS_DCSRBAR 0xf0000000
156 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
160 #define CONFIG_ID_EEPROM
161 #define CONFIG_SYS_I2C_EEPROM_NXID
162 #define CONFIG_SYS_EEPROM_BUS_NUM 0
163 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
164 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
169 #define CONFIG_VERY_BIG_RAM
170 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
171 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
173 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
174 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
176 #define CONFIG_DDR_SPD
177 #define CONFIG_FSL_DDR3
179 #define CONFIG_SYS_SPD_BUS_NUM 1
180 #define SPD_EEPROM_ADDRESS1 0x51
181 #define SPD_EEPROM_ADDRESS2 0x52
182 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */
183 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
186 * Local Bus Definitions
189 /* Set the local bus clock 1/8 of platform clock */
190 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8
192 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* Start of PromJet */
193 #ifdef CONFIG_PHYS_64BIT
194 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
196 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
199 #define CONFIG_SYS_BR0_PRELIM \
200 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | \
202 #define CONFIG_SYS_OR0_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
203 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
205 #define CONFIG_SYS_BR1_PRELIM \
206 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
207 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
209 #define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */
210 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
211 #ifdef CONFIG_PHYS_64BIT
212 #define PIXIS_BASE_PHYS 0xfffdf0000ull
214 #define PIXIS_BASE_PHYS PIXIS_BASE
217 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
218 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
220 #define PIXIS_LBMAP_SWITCH 7
221 #define PIXIS_LBMAP_MASK 0xf0
222 #define PIXIS_LBMAP_SHIFT 4
223 #define PIXIS_LBMAP_ALTBANK 0x40
225 #define CONFIG_SYS_FLASH_QUIET_TEST
226 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
228 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
229 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
230 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
231 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
233 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
235 #if defined(CONFIG_RAMBOOT_PBL)
236 #define CONFIG_SYS_RAMBOOT
240 #if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS)
241 #define CONFIG_NAND_FSL_ELBC
242 #ifdef CONFIG_NAND_FSL_ELBC
243 #define CONFIG_SYS_NAND_BASE 0xffa00000
244 #ifdef CONFIG_PHYS_64BIT
245 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
247 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
250 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
251 #define CONFIG_SYS_MAX_NAND_DEVICE 1
252 #define CONFIG_MTD_NAND_VERIFY_WRITE
253 #define CONFIG_CMD_NAND
254 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
256 /* NAND flash config */
257 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
258 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
259 | BR_PS_8 /* Port Size = 8 bit */ \
260 | BR_MS_FCM /* MSEL = FCM */ \
262 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
263 | OR_FCM_PGS /* Large Page*/ \
271 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
272 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
273 #endif /* CONFIG_NAND_FSL_ELBC */
276 #define CONFIG_SYS_FLASH_EMPTY_INFO
277 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
278 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
280 #define CONFIG_BOARD_EARLY_INIT_F
281 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
282 #define CONFIG_MISC_INIT_R
284 #define CONFIG_HWCONFIG
286 /* define to use L1 as initial stack */
287 #define CONFIG_L1_INIT_RAM
288 #define CONFIG_SYS_INIT_RAM_LOCK
289 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
290 #ifdef CONFIG_PHYS_64BIT
291 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
292 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
293 /* The assembler doesn't like typecast */
294 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
295 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
296 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
298 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
299 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
300 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
302 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
304 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
305 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
307 #define CONFIG_SYS_MONITOR_LEN (512 * 1024)
308 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
310 /* Serial Port - controlled on board with jumper J8
314 #define CONFIG_CONS_INDEX 1
315 #define CONFIG_SYS_NS16550
316 #define CONFIG_SYS_NS16550_SERIAL
317 #define CONFIG_SYS_NS16550_REG_SIZE 1
318 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
320 #define CONFIG_SYS_BAUDRATE_TABLE \
321 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
323 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
324 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
325 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
326 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
328 /* Use the HUSH parser */
329 #define CONFIG_SYS_HUSH_PARSER
330 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
332 /* pass open firmware flat tree */
333 #define CONFIG_OF_LIBFDT
334 #define CONFIG_OF_BOARD_SETUP
335 #define CONFIG_OF_STDOUT_VIA_ALIAS
337 /* new uImage format support */
339 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
342 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */
343 #define CONFIG_HARD_I2C /* I2C with hardware support */
344 #define CONFIG_I2C_MULTI_BUS
345 #define CONFIG_I2C_CMD_TREE
346 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
347 #define CONFIG_SYS_I2C_SLAVE 0x7F
348 #define CONFIG_SYS_I2C_OFFSET 0x118000
349 #define CONFIG_SYS_I2C2_OFFSET 0x118100
354 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
355 #ifdef CONFIG_PHYS_64BIT
356 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
358 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
360 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
362 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
363 #ifdef CONFIG_PHYS_64BIT
364 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
366 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000
368 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
371 * eSPI - Enhanced SPI
373 #define CONFIG_FSL_ESPI
374 #define CONFIG_SPI_FLASH
375 #define CONFIG_SPI_FLASH_SPANSION
376 #define CONFIG_CMD_SF
377 #define CONFIG_SF_DEFAULT_SPEED 10000000
378 #define CONFIG_SF_DEFAULT_MODE 0
382 * Memory space is mapped 1-1, but I/O space must start from 0.
385 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
386 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
387 #ifdef CONFIG_PHYS_64BIT
388 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
389 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
391 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
392 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
394 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
395 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
396 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
397 #ifdef CONFIG_PHYS_64BIT
398 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
400 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
402 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
404 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
405 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
406 #ifdef CONFIG_PHYS_64BIT
407 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
408 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
410 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
411 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
413 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
414 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
415 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
416 #ifdef CONFIG_PHYS_64BIT
417 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
419 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000
421 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
423 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
424 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
425 #ifdef CONFIG_PHYS_64BIT
426 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
427 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
429 #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000
430 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000
432 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
433 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
434 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
435 #ifdef CONFIG_PHYS_64BIT
436 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
438 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000
440 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
442 /* controller 4, Base address 203000 */
443 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
444 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
445 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */
446 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
447 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
448 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
451 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
452 #define CONFIG_SYS_BMAN_NUM_PORTALS 10
453 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
454 #ifdef CONFIG_PHYS_64BIT
455 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
457 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
459 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
460 #define CONFIG_SYS_QMAN_NUM_PORTALS 10
461 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
462 #ifdef CONFIG_PHYS_64BIT
463 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
465 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
467 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
469 #define CONFIG_SYS_DPAA_FMAN
470 #define CONFIG_SYS_DPAA_PME
471 /* Default address of microcode for the Linux Fman driver */
472 #define CONFIG_SYS_FMAN_FW_ADDR 0xEF000000
473 #ifdef CONFIG_PHYS_64BIT
474 #define CONFIG_SYS_FMAN_FW_ADDR_PHYS 0xFEF000000ULL
476 #define CONFIG_SYS_FMAN_FW_ADDR_PHYS CONFIG_SYS_FMAN_FW_ADDR
479 #ifdef CONFIG_SYS_DPAA_FMAN
480 #define CONFIG_FMAN_ENET
484 #define CONFIG_NET_MULTI
485 #define CONFIG_PCI_PNP /* do pci plug-and-play */
488 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
489 #define CONFIG_DOS_PARTITION
490 #endif /* CONFIG_PCI */
493 #ifdef CONFIG_FSL_SATA_V2
494 #define CONFIG_LIBATA
495 #define CONFIG_FSL_SATA
497 #define CONFIG_SYS_SATA_MAX_DEVICE 2
499 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
500 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
502 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
503 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
506 #define CONFIG_CMD_SATA
507 #define CONFIG_DOS_PARTITION
508 #define CONFIG_CMD_EXT2
511 #ifdef CONFIG_FMAN_ENET
512 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1c
513 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x1d
514 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x1e
515 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1f
516 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4
518 #define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR 0x1c
519 #define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR 0x1d
520 #define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR 0x1e
521 #define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR 0x1f
522 #define CONFIG_SYS_FM2_10GEC1_PHY_ADDR 0
524 #define CONFIG_SYS_TBIPA_VALUE 8
525 #define CONFIG_MII /* MII PHY management */
526 #define CONFIG_ETHPRIME "FM1@DTSEC1"
527 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
533 #define CONFIG_LOADS_ECHO /* echo on for serial download */
534 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
537 * Command line configuration.
539 #include <config_cmd_default.h>
541 #define CONFIG_CMD_DHCP
542 #define CONFIG_CMD_ELF
543 #define CONFIG_CMD_ERRATA
544 #define CONFIG_CMD_GREPENV
545 #define CONFIG_CMD_IRQ
546 #define CONFIG_CMD_I2C
547 #define CONFIG_CMD_MII
548 #define CONFIG_CMD_PING
549 #define CONFIG_CMD_SETEXPR
552 #define CONFIG_CMD_PCI
553 #define CONFIG_CMD_NET
559 #define CONFIG_CMD_USB
560 #define CONFIG_USB_STORAGE
561 #define CONFIG_USB_EHCI
562 #define CONFIG_USB_EHCI_FSL
563 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
564 #define CONFIG_CMD_EXT2
569 #define CONFIG_FSL_ESDHC
570 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
571 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
572 #define CONFIG_CMD_MMC
573 #define CONFIG_GENERIC_MMC
574 #define CONFIG_CMD_EXT2
575 #define CONFIG_CMD_FAT
576 #define CONFIG_DOS_PARTITION
580 * Miscellaneous configurable options
582 #define CONFIG_SYS_LONGHELP /* undef to save memory */
583 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
584 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
585 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
586 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
587 #ifdef CONFIG_CMD_KGDB
588 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
590 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
592 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
593 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
594 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
595 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
598 * For booting Linux, the board info and command line data
599 * have to be in the first 64 MB of memory, since this is
600 * the maximum mapped by the Linux kernel during initialization.
602 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
603 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
605 #ifdef CONFIG_CMD_KGDB
606 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
607 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
611 * Environment Configuration
613 #define CONFIG_ROOTPATH /opt/nfsroot
614 #define CONFIG_BOOTFILE uImage
615 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
617 /* default location for tftp and bootm */
618 #define CONFIG_LOADADDR 1000000
620 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
622 #define CONFIG_BAUDRATE 115200
624 #define CONFIG_EXTRA_ENV_SETTINGS \
625 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
626 "bank_intlv=cs0_cs1\0" \
628 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
629 "ubootaddr=" MK_STR(CONFIG_SYS_TEXT_BASE) "\0" \
630 "tftpflash=tftpboot $loadaddr $uboot && " \
631 "protect off $ubootaddr +$filesize && " \
632 "erase $ubootaddr +$filesize && " \
633 "cp.b $loadaddr $ubootaddr $filesize && " \
634 "protect on $ubootaddr +$filesize && " \
635 "cmp.b $loadaddr $ubootaddr $filesize\0" \
636 "consoledev=ttyS0\0" \
637 "ramdiskaddr=2000000\0" \
638 "ramdiskfile=p4080ds/ramdisk.uboot\0" \
640 "fdtfile=p4080ds/p4080ds.dtb\0" \
643 "fman_ucode="MK_STR(CONFIG_SYS_FMAN_FW_ADDR_PHYS)"\0"
645 #define CONFIG_HDBOOT \
646 "setenv bootargs root=/dev/$bdev rw " \
647 "console=$consoledev,$baudrate $othbootargs;" \
648 "tftp $loadaddr $bootfile;" \
649 "tftp $fdtaddr $fdtfile;" \
650 "bootm $loadaddr - $fdtaddr"
652 #define CONFIG_NFSBOOTCOMMAND \
653 "setenv bootargs root=/dev/nfs rw " \
654 "nfsroot=$serverip:$rootpath " \
655 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
656 "console=$consoledev,$baudrate $othbootargs;" \
657 "tftp $loadaddr $bootfile;" \
658 "tftp $fdtaddr $fdtfile;" \
659 "bootm $loadaddr - $fdtaddr"
661 #define CONFIG_RAMBOOTCOMMAND \
662 "setenv bootargs root=/dev/ram rw " \
663 "console=$consoledev,$baudrate $othbootargs;" \
664 "tftp $ramdiskaddr $ramdiskfile;" \
665 "tftp $loadaddr $bootfile;" \
666 "tftp $fdtaddr $fdtfile;" \
667 "bootm $loadaddr $ramdiskaddr $fdtaddr"
669 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
671 #endif /* __CONFIG_H */