2 * Copyright 2009-2011 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * Corenet DS style board configuration file
29 #include "../board/freescale/common/ics307_clk.h"
31 /* High Level Configuration Options */
33 #define CONFIG_E500 /* BOOKE e500 family */
34 #define CONFIG_E500MC /* BOOKE e500mc family */
35 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
36 #define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */
37 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
38 #define CONFIG_MP /* support multiple processors */
40 #ifndef CONFIG_SYS_TEXT_BASE
41 #define CONFIG_SYS_TEXT_BASE 0xeff80000
44 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
45 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
46 #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
47 #define CONFIG_PCI /* Enable PCI/PCIE */
48 #define CONFIG_PCIE1 /* PCIE controler 1 */
49 #define CONFIG_PCIE2 /* PCIE controler 2 */
50 #define CONFIG_PCIE3 /* PCIE controler 3 */
51 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
52 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
54 #define CONFIG_SYS_SRIO
55 #define CONFIG_SRIO1 /* SRIO port 1 */
56 #define CONFIG_SRIO2 /* SRIO port 2 */
58 #define CONFIG_FSL_LAW /* Use common FSL init code */
60 #define CONFIG_ENV_OVERWRITE
62 #ifdef CONFIG_SYS_NO_FLASH
63 #define CONFIG_ENV_IS_NOWHERE
65 #define CONFIG_ENV_IS_IN_FLASH
66 #define CONFIG_FLASH_CFI_DRIVER
67 #define CONFIG_SYS_FLASH_CFI
70 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
73 * These can be toggled for performance analysis, otherwise use default.
75 #define CONFIG_SYS_CACHE_STASHING
76 #define CONFIG_BACKSIDE_L2_CACHE
77 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
78 #define CONFIG_BTB /* toggle branch predition */
79 /*#define CONFIG_DDR_ECC*/
81 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
82 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
85 #define CONFIG_ENABLE_36BIT_PHYS
87 #ifdef CONFIG_PHYS_64BIT
88 #define CONFIG_ADDR_MAP
89 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
92 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
93 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
94 #define CONFIG_SYS_MEMTEST_END 0x00400000
95 #define CONFIG_SYS_ALT_MEMTEST
96 #define CONFIG_PANIC_HANG /* do not reset board on panic */
99 * Base addresses -- Note these are effective addresses where the
100 * actual resources get mapped (not physical addresses)
102 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 /* CCSRBAR Default */
103 #define CONFIG_SYS_CCSRBAR 0xfe000000 /* relocated CCSRBAR */
104 #ifdef CONFIG_PHYS_64BIT
105 #define CONFIG_SYS_CCSRBAR_PHYS 0xffe000000ull /* physical addr of CCSRBAR */
107 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
109 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
111 #ifdef CONFIG_PHYS_64BIT
112 #define CONFIG_SYS_DCSRBAR 0xf0000000
113 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
117 #define CONFIG_ID_EEPROM
118 #define CONFIG_SYS_I2C_EEPROM_NXID
119 #define CONFIG_SYS_EEPROM_BUS_NUM 0
120 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
121 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
126 #define CONFIG_VERY_BIG_RAM
127 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
128 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
130 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
131 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
133 #define CONFIG_DDR_SPD
134 #define CONFIG_FSL_DDR3
136 #define CONFIG_SYS_SPD_BUS_NUM 1
137 #define SPD_EEPROM_ADDRESS1 0x51
138 #define SPD_EEPROM_ADDRESS2 0x52
139 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
142 * Local Bus Definitions
145 /* Set the local bus clock 1/8 of platform clock */
146 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8
148 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* Start of PromJet */
149 #ifdef CONFIG_PHYS_64BIT
150 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
152 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
155 #define CONFIG_SYS_BR0_PRELIM \
156 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | \
158 #define CONFIG_SYS_OR0_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
159 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
161 #define CONFIG_SYS_BR1_PRELIM \
162 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
163 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
165 #define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */
166 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
167 #ifdef CONFIG_PHYS_64BIT
168 #define PIXIS_BASE_PHYS 0xfffdf0000ull
170 #define PIXIS_BASE_PHYS PIXIS_BASE
173 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
174 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
176 #define PIXIS_LBMAP_SWITCH 7
177 #define PIXIS_LBMAP_MASK 0xf0
178 #define PIXIS_LBMAP_SHIFT 4
179 #define PIXIS_LBMAP_ALTBANK 0x40
181 #define CONFIG_SYS_FLASH_QUIET_TEST
182 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
184 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
185 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
186 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
187 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
189 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
191 #define CONFIG_SYS_FLASH_EMPTY_INFO
192 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
193 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
195 #define CONFIG_BOARD_EARLY_INIT_F
196 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
197 #define CONFIG_MISC_INIT_R
199 #define CONFIG_HWCONFIG
201 /* define to use L1 as initial stack */
202 #define CONFIG_L1_INIT_RAM
203 #define CONFIG_SYS_INIT_RAM_LOCK
204 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
205 #ifdef CONFIG_PHYS_64BIT
206 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
207 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
208 /* The assembler doesn't like typecast */
209 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
210 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
211 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
213 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
214 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
215 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
217 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
219 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
220 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
222 #define CONFIG_SYS_MONITOR_LEN (512 * 1024)
223 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
225 /* Serial Port - controlled on board with jumper J8
229 #define CONFIG_CONS_INDEX 1
230 #define CONFIG_SYS_NS16550
231 #define CONFIG_SYS_NS16550_SERIAL
232 #define CONFIG_SYS_NS16550_REG_SIZE 1
233 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
235 #define CONFIG_SYS_BAUDRATE_TABLE \
236 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
238 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
239 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
240 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
241 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
243 /* Use the HUSH parser */
244 #define CONFIG_SYS_HUSH_PARSER
245 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
247 /* pass open firmware flat tree */
248 #define CONFIG_OF_LIBFDT
249 #define CONFIG_OF_BOARD_SETUP
250 #define CONFIG_OF_STDOUT_VIA_ALIAS
252 /* new uImage format support */
254 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
257 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */
258 #define CONFIG_HARD_I2C /* I2C with hardware support */
259 #define CONFIG_I2C_MULTI_BUS
260 #define CONFIG_I2C_CMD_TREE
261 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
262 #define CONFIG_SYS_I2C_SLAVE 0x7F
263 #define CONFIG_SYS_I2C_OFFSET 0x118000
264 #define CONFIG_SYS_I2C2_OFFSET 0x118100
269 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
270 #ifdef CONFIG_PHYS_64BIT
271 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
273 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
275 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
277 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
278 #ifdef CONFIG_PHYS_64BIT
279 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
281 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000
283 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
287 * Memory space is mapped 1-1, but I/O space must start from 0.
290 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
291 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
292 #ifdef CONFIG_PHYS_64BIT
293 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
294 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
296 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
297 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
299 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
300 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
301 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
302 #ifdef CONFIG_PHYS_64BIT
303 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
305 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
307 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
309 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
310 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
311 #ifdef CONFIG_PHYS_64BIT
312 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
313 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
315 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
316 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
318 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
319 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
320 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
321 #ifdef CONFIG_PHYS_64BIT
322 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
324 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000
326 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
328 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
329 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xe0000000
330 #ifdef CONFIG_PHYS_64BIT
331 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
332 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
334 #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000
335 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000
337 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
338 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
339 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
340 #ifdef CONFIG_PHYS_64BIT
341 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
343 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000
345 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
347 /* controller 4, Base address 203000 */
348 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
349 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
350 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */
351 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
352 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
353 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
356 #define CONFIG_SYS_BMAN_NUM_PORTALS 10
357 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
358 #ifdef CONFIG_PHYS_64BIT
359 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
361 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
363 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
364 #define CONFIG_SYS_QMAN_NUM_PORTALS 10
365 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
366 #ifdef CONFIG_PHYS_64BIT
367 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
369 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
371 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
373 #define CONFIG_SYS_DPAA_FMAN
374 #define CONFIG_SYS_DPAA_PME
375 /* Default address of microcode for the Linux Fman driver */
376 #define CONFIG_SYS_FMAN_FW_ADDR 0xEF000000
377 #ifdef CONFIG_PHYS_64BIT
378 #define CONFIG_SYS_FMAN_FW_ADDR_PHYS 0xFEF000000ULL
380 #define CONFIG_SYS_FMAN_FW_ADDR_PHYS CONFIG_SYS_FMAN_FW_ADDR
383 #ifdef CONFIG_SYS_DPAA_FMAN
384 #define CONFIG_FMAN_ENET
389 /*PCIE video card used*/
390 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT
396 #define CONFIG_BIOSEMU
397 #define CONFIG_CFB_CONSOLE
398 #define CONFIG_VIDEO_SW_CURSOR
399 #define CONFIG_VGA_AS_SINGLE_DEVICE
400 #define CONFIG_ATI_RADEON_FB
401 #define CONFIG_VIDEO_LOGO
402 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
405 #define CONFIG_NET_MULTI
406 #define CONFIG_PCI_PNP /* do pci plug-and-play */
409 #ifndef CONFIG_PCI_PNP
410 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS
411 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS
412 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */
415 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
416 #define CONFIG_DOS_PARTITION
417 #endif /* CONFIG_PCI */
420 #ifdef CONFIG_FSL_SATA_V2
421 #define CONFIG_LIBATA
422 #define CONFIG_FSL_SATA
424 #define CONFIG_SYS_SATA_MAX_DEVICE 2
426 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
427 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
429 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
430 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
433 #define CONFIG_CMD_SATA
434 #define CONFIG_DOS_PARTITION
435 #define CONFIG_CMD_EXT2
438 #ifdef CONFIG_FMAN_ENET
439 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1c
440 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x1d
441 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x1e
442 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1f
443 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4
445 #if (CONFIG_SYS_NUM_FMAN == 2)
446 #define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR 0x1c
447 #define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR 0x1d
448 #define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR 0x1e
449 #define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR 0x1f
450 #define CONFIG_SYS_FM2_10GEC1_PHY_ADDR 0
453 #define CONFIG_SYS_TBIPA_VALUE 8
454 #define CONFIG_MII /* MII PHY management */
455 #define CONFIG_ETHPRIME "FM1@DTSEC1"
456 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
462 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
463 #define CONFIG_ENV_SIZE 0x2000
464 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
466 #define CONFIG_LOADS_ECHO /* echo on for serial download */
467 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
470 * Command line configuration.
472 #include <config_cmd_default.h>
474 #define CONFIG_CMD_ELF
475 #define CONFIG_CMD_ERRATA
476 #define CONFIG_CMD_IRQ
477 #define CONFIG_CMD_I2C
478 #define CONFIG_CMD_MII
479 #define CONFIG_CMD_PING
480 #define CONFIG_CMD_SETEXPR
481 #define CONFIG_CMD_DHCP
484 #define CONFIG_CMD_PCI
485 #define CONFIG_CMD_NET
491 #define CONFIG_CMD_USB
492 #define CONFIG_USB_STORAGE
493 #define CONFIG_USB_EHCI
494 #define CONFIG_USB_EHCI_FSL
495 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
496 #define CONFIG_CMD_EXT2
501 #define CONFIG_FSL_ESDHC
502 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
503 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
504 #define CONFIG_CMD_MMC
505 #define CONFIG_GENERIC_MMC
506 #define CONFIG_CMD_EXT2
507 #define CONFIG_CMD_FAT
508 #define CONFIG_DOS_PARTITION
512 * Miscellaneous configurable options
514 #define CONFIG_SYS_LONGHELP /* undef to save memory */
515 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
516 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
517 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
518 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
519 #ifdef CONFIG_CMD_KGDB
520 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
522 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
524 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
525 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
526 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
527 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
530 * For booting Linux, the board info and command line data
531 * have to be in the first 16 MB of memory, since this is
532 * the maximum mapped by the Linux kernel during initialization.
534 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
535 #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
537 #ifdef CONFIG_CMD_KGDB
538 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
539 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
543 * Environment Configuration
545 #define CONFIG_ROOTPATH /opt/nfsroot
546 #define CONFIG_BOOTFILE uImage
547 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
549 /* default location for tftp and bootm */
550 #define CONFIG_LOADADDR 1000000
552 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
554 #define CONFIG_BAUDRATE 115200
556 #define CONFIG_EXTRA_ENV_SETTINGS \
557 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
558 "bank_intlv=cs0_cs1\0" \
560 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
561 "ubootaddr=" MK_STR(CONFIG_SYS_TEXT_BASE) "\0" \
562 "tftpflash=tftpboot $loadaddr $uboot && " \
563 "protect off $ubootaddr +$filesize && " \
564 "erase $ubootaddr +$filesize && " \
565 "cp.b $loadaddr $ubootaddr $filesize && " \
566 "protect on $ubootaddr +$filesize && " \
567 "cmp.b $loadaddr $ubootaddr $filesize\0" \
568 "consoledev=ttyS0\0" \
569 "ramdiskaddr=2000000\0" \
570 "ramdiskfile=p4080ds/ramdisk.uboot\0" \
572 "fdtfile=p4080ds/p4080ds.dtb\0" \
575 "fman_ucode="MK_STR(CONFIG_SYS_FMAN_FW_ADDR_PHYS)"\0"
577 #define CONFIG_HDBOOT \
578 "setenv bootargs root=/dev/$bdev rw " \
579 "console=$consoledev,$baudrate $othbootargs;" \
580 "tftp $loadaddr $bootfile;" \
581 "tftp $fdtaddr $fdtfile;" \
582 "bootm $loadaddr - $fdtaddr"
584 #define CONFIG_NFSBOOTCOMMAND \
585 "setenv bootargs root=/dev/nfs rw " \
586 "nfsroot=$serverip:$rootpath " \
587 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
588 "console=$consoledev,$baudrate $othbootargs;" \
589 "tftp $loadaddr $bootfile;" \
590 "tftp $fdtaddr $fdtfile;" \
591 "bootm $loadaddr - $fdtaddr"
593 #define CONFIG_RAMBOOTCOMMAND \
594 "setenv bootargs root=/dev/ram rw " \
595 "console=$consoledev,$baudrate $othbootargs;" \
596 "tftp $ramdiskaddr $ramdiskfile;" \
597 "tftp $loadaddr $bootfile;" \
598 "tftp $fdtaddr $fdtfile;" \
599 "bootm $loadaddr $ramdiskaddr $fdtaddr"
601 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
603 #endif /* __CONFIG_H */