2 * (C) Copyright 2003-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 /*************************************************************************
26 * (c) 2005 esd gmbh Hannover
30 * by Reinhard Arlt reinhard.arlt@esd-electronics.com
32 *************************************************************************/
38 * High Level Configuration Options
42 #define CONFIG_MPC5200 1 /* This is an MPC5xxx CPU */
43 #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
44 #define CONFIG_ICECUBE 1 /* ... on IceCube board */
45 #define CONFIG_CPCI5200 1 /* ... on CPCI5200 board */
46 #define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */
48 #define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
50 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
51 #define BOOTFLAG_WARM 0x02 /* Software reboot */
54 * Serial console configuration
56 #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
57 #define CONFIG_BAUDRATE 9600 /* ... at 115200 bps */
58 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
60 #ifdef CONFIG_MPC5200 /* MPC5100 PCI is not supported yet. */
63 * 0x40000000 - 0x4fffffff - PCI Memory
64 * 0x50000000 - 0x50ffffff - PCI IO Space
69 #define CONFIG_PCI_PNP 1
71 #define CONFIG_PCI_SCAN_SHOW 1
73 #define CONFIG_PCI_MEM_BUS 0x40000000
74 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
75 #define CONFIG_PCI_MEM_SIZE 0x10000000
77 #define CONFIG_PCI_IO_BUS 0x50000000
78 #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
79 #define CONFIG_PCI_IO_SIZE 0x01000000
83 #if 0 /* test-only !!! */
84 #define CONFIG_NET_MULTI 1
85 #define CONFIG_EEPRO100 1
86 #define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
87 #define CONFIG_NS8382X 1
93 #define CONFIG_MAC_PARTITION
94 #define CONFIG_DOS_PARTITION
98 #define CONFIG_USB_OHCI
99 #define CONFIG_USB_STORAGE
103 * Command line configuration.
105 #include <config_cmd_default.h>
107 #if defined(CONFIG_PCI)
108 #define CONFIG_CMD_PCI
111 #define CONFIG_CMD_EEPROM
112 #define CONFIG_CMD_FAT
113 #define CONFIG_CMD_IDE
114 #define CONFIG_CMD_I2C
115 #define CONFIG_CMD_BSP
116 #define CONFIG_CMD_ELF
117 #define CONFIG_CMD_EXT2
118 #define CONFIG_CMD_DATE
120 #if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
121 # define CFG_LOWBOOT 1
122 # define CFG_LOWBOOT16 1
124 #if (TEXT_BASE == 0xFF800000) /* Boot low with 8 MB Flash */
125 # define CFG_LOWBOOT 1
126 # define CFG_LOWBOOT08 1
132 #define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
134 #define CONFIG_PREBOOT "echo;" \
135 "echo Welcome to esd CPU CPCI/5200;" \
138 #undef CONFIG_BOOTARGS
140 #define CONFIG_EXTRA_ENV_SETTINGS \
142 "flash_vxworks0=run ata_vxworks_args;setenv loadaddr ff000000;bootvx\0" \
143 "flash_vxworks1=run ata_vxworks_args;setenv loadaddr ff200000:bootvx\0" \
144 "net_vxworks=phypower 1;sleep 2;tftp ${loadaddr} ${image};run vxworks_args;bootvx\0" \
145 "vxworks_args=setenv bootargs fec(0,0)${host}:${image} h=${serverip} e=${ipaddr} g=${gatewayip} u=${user} ${pass} tn=${target} s=${script}\0" \
146 "ata_vxworks_args=setenv bootargs /ata0/vxWorks h=${serverip} e=${ipaddr} g=${gatewayip} u=${user} ${pass} tn=${target} s=${script} o=fec0 \0" \
147 "loadaddr=01000000\0" \
148 "serverip=192.168.2.99\0" \
149 "gatewayip=10.0.0.79\0" \
151 "target=cpci5200.esd\0" \
152 "script=cpci5200.bat\0" \
153 "image=/tftpboot/vxWorks_cpci5200\0" \
154 "ipaddr=10.0.13.196\0" \
155 "netmask=255.255.0.0\0" \
158 #define CONFIG_BOOTCOMMAND "run flash_vxworks0"
160 #if defined(CONFIG_MPC5200)
162 #define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */
163 #define CFG_NVRAM_BASE_ADDR 0xfd010000
164 #define CFG_NVRAM_SIZE 32*1024
167 * IPB Bus clocking configuration.
169 #undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
174 #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
175 #define CFG_I2C_MODULE 1 /* Select I2C module #1 or #2 */
177 #define CFG_I2C_SPEED 86000 /* 100 kHz */
178 #define CFG_I2C_SLAVE 0x7F
181 * EEPROM configuration
183 #define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */
184 #define CFG_I2C_EEPROM_ADDR_LEN 2
185 #define CFG_EEPROM_PAGE_WRITE_BITS 5
186 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20
187 #define CFG_I2C_MULTI_EEPROMS 1
189 * Flash configuration
192 #define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
193 #define CFG_FLASH_BASE 0xFE000000
194 #define CFG_FLASH_SIZE 0x02000000
195 #define CFG_FLASH_INCREMENT 0x01000000
196 #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00000000)
197 #define CFG_MAX_FLASH_BANKS 2 /* max num of memory banks */
198 #define CFG_MAX_FLASH_SECT 128
200 #define CFG_FLASH_PROTECTION 1 /* use hardware protection */
201 #define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
203 #define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
204 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
207 * Environment settings
209 #if 1 /* test-only */
210 #define CFG_ENV_IS_IN_FLASH 1
211 #define CFG_ENV_SIZE 0x20000
212 #define CFG_ENV_SECT_SIZE 0x20000
213 #define CONFIG_ENV_OVERWRITE 1
215 #define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
216 #define CFG_ENV_OFFSET 0x0000 /* environment starts at the beginning of the EEPROM */
217 #define CFG_ENV_SIZE 0x0400 /* 8192 bytes may be used for env vars */
218 /* total size of a CAT24WC32 is 8192 bytes */
219 #define CONFIG_ENV_OVERWRITE 1
225 #define CFG_MBAR 0xF0000000
226 #define CFG_SDRAM_BASE 0x00000000
227 #define CFG_DEFAULT_MBAR 0x80000000
229 /* Use SRAM until RAM will be available */
230 #define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
231 #define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */
233 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
234 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
235 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
237 #define CFG_MONITOR_BASE TEXT_BASE
238 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
239 # define CFG_RAMBOOT 1
242 #define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
243 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
244 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
247 * Ethernet configuration
249 #define CONFIG_MPC5xxx_FEC 1
251 * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
253 /* #define CONFIG_FEC_10MBIT 1 */
254 #define CONFIG_PHY_ADDR 0x00
255 #define CONFIG_UDP_CHECKSUM 1
260 #define CFG_GPS_PORT_CONFIG 0x01052444
263 * Miscellaneous configurable options
265 #define CFG_LONGHELP /* undef to save memory */
266 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
267 #if defined(CONFIG_CMD_KGDB)
268 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
270 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
272 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
273 #define CFG_MAXARGS 16 /* max number of command args */
274 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
276 #define CFG_MEMTEST_START 0x00100000 /* memtest works on */
277 #define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
279 #define CFG_LOAD_ADDR 0x100000 /* default load address */
281 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
283 #define CFG_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */
285 #define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
286 #if defined(CONFIG_CMD_KGDB)
287 # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
291 * Various low-level settings
293 #if defined(CONFIG_MPC5200)
294 #define CFG_HID0_INIT HID0_ICE | HID0_ICFI
295 #define CFG_HID0_FINAL HID0_ICE
297 #define CFG_HID0_INIT 0
298 #define CFG_HID0_FINAL 0
301 #define CFG_BOOTCS_START CFG_FLASH_BASE
302 #define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
303 #define CFG_BOOTCS_CFG 0x0004DD00
305 #define CFG_CS0_START CFG_FLASH_BASE
306 #define CFG_CS0_SIZE CFG_FLASH_SIZE
308 #define CFG_CS1_START 0xfd000000
309 #define CFG_CS1_SIZE 0x00010000
310 #define CFG_CS1_CFG 0x10101410
312 #define CFG_CS3_START 0xfd010000
313 #define CFG_CS3_SIZE 0x00010000
314 #define CFG_CS3_CFG 0x10109410
316 #define CFG_CS_BURST 0x00000000
317 #define CFG_CS_DEADCYCLE 0x33333333
319 #define CFG_RESET_ADDRESS 0xff000000
321 /*-----------------------------------------------------------------------
323 *-----------------------------------------------------------------------
325 #define CONFIG_USB_CLOCK 0x0001BBBB
326 #define CONFIG_USB_CONFIG 0x00001000
328 /*-----------------------------------------------------------------------
329 * IDE/ATA stuff Supports IDE harddisk
330 *-----------------------------------------------------------------------
333 #undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
335 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
336 #undef CONFIG_IDE_LED /* LED for ide not supported */
338 #define CONFIG_IDE_RESET /* reset for ide supported */
339 #define CONFIG_IDE_PREINIT
341 #define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
342 #define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
344 #define CFG_ATA_IDE0_OFFSET 0x0000
346 #define CFG_ATA_BASE_ADDR MPC5XXX_ATA
348 /* Offset for data I/O */
349 #define CFG_ATA_DATA_OFFSET (0x0060)
351 /* Offset for normal register accesses */
352 #define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET)
354 /* Offset for alternate registers */
355 #define CFG_ATA_ALT_OFFSET (0x005C)
357 /* Interval between registers */
358 #define CFG_ATA_STRIDE 4
360 /*-----------------------------------------------------------------------
363 #define CFG_FPGA_XC95XL 1 /* using Xilinx XC95XL CPLD */
364 #define CFG_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for CPLD */
366 /* CPLD program pin configuration */
367 #define CFG_FPGA_PRG 0x20000000 /* JTAG TMS pin (ppc output) */
368 #define CFG_FPGA_CLK 0x10000000 /* JTAG TCK pin (ppc output) */
369 #define CFG_FPGA_DATA 0x20000000 /* JTAG TDO->TDI data pin (ppc output) */
370 #define CFG_FPGA_DONE 0x10000000 /* JTAG TDI->TDO pin (ppc input) */
372 #define JTAG_GPIO_ADDR_TMS (CFG_MBAR + 0xB10) /* JTAG TMS pin (GPS data out value reg.) */
373 #define JTAG_GPIO_ADDR_TCK (CFG_MBAR + 0xC0C) /* JTAG TCK pin (GPW data out value reg.) */
374 #define JTAG_GPIO_ADDR_TDI (CFG_MBAR + 0xC0C) /* JTAG TDO->TDI pin (GPW data out value reg.) */
375 #define JTAG_GPIO_ADDR_TDO (CFG_MBAR + 0xB14) /* JTAG TDI->TDO pin (GPS data in value reg.) */
377 #define JTAG_GPIO_ADDR_CFG (CFG_MBAR + 0xB00)
378 #define JTAG_GPIO_CFG_SET 0x00000000
379 #define JTAG_GPIO_CFG_RESET 0x00F00000
381 #define JTAG_GPIO_ADDR_EN_TMS (CFG_MBAR + 0xB04)
382 #define JTAG_GPIO_TMS_EN_SET 0x20000000 /* Enable for GPIO */
383 #define JTAG_GPIO_TMS_EN_RESET 0x00000000
384 #define JTAG_GPIO_ADDR_DDR_TMS (CFG_MBAR + 0xB0C)
385 #define JTAG_GPIO_TMS_DDR_SET 0x20000000 /* Set as output */
386 #define JTAG_GPIO_TMS_DDR_RESET 0x00000000
388 #define JTAG_GPIO_ADDR_EN_TCK (CFG_MBAR + 0xC00)
389 #define JTAG_GPIO_TCK_EN_SET 0x20000000 /* Enable for GPIO */
390 #define JTAG_GPIO_TCK_EN_RESET 0x00000000
391 #define JTAG_GPIO_ADDR_DDR_TCK (CFG_MBAR + 0xC08)
392 #define JTAG_GPIO_TCK_DDR_SET 0x20000000 /* Set as output */
393 #define JTAG_GPIO_TCK_DDR_RESET 0x00000000
395 #define JTAG_GPIO_ADDR_EN_TDI (CFG_MBAR + 0xC00)
396 #define JTAG_GPIO_TDI_EN_SET 0x10000000 /* Enable as GPIO */
397 #define JTAG_GPIO_TDI_EN_RESET 0x00000000
398 #define JTAG_GPIO_ADDR_DDR_TDI (CFG_MBAR + 0xC08)
399 #define JTAG_GPIO_TDI_DDR_SET 0x10000000 /* Set as output */
400 #define JTAG_GPIO_TDI_DDR_RESET 0x00000000
402 #define JTAG_GPIO_ADDR_EN_TDO (CFG_MBAR + 0xB04)
403 #define JTAG_GPIO_TDO_EN_SET 0x10000000 /* Enable as GPIO */
404 #define JTAG_GPIO_TDO_EN_RESET 0x00000000
405 #define JTAG_GPIO_ADDR_DDR_TDO (CFG_MBAR + 0xB0C)
406 #define JTAG_GPIO_TDO_DDR_SET 0x00000000
407 #define JTAG_GPIO_TDO_DDR_RESET 0x10000000 /* Set as input */
409 #endif /* __CONFIG_H */