1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Based on corenet_ds.h
9 #if !defined(CONFIG_ARCH_P5020) && !defined(CONFIG_ARCH_P5040)
10 #error Must call Cyrus CONFIG with a specific CPU enabled.
14 #define CONFIG_FSL_SATA_V2
17 #ifdef CONFIG_ARCH_P5020
18 #define CONFIG_SYS_FSL_RAID_ENGINE
19 #define CONFIG_SYS_DPAA_RMAN
21 #define CONFIG_SYS_DPAA_PME
24 * Corenet DS style board configuration file
26 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
27 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
28 #define CONFIG_SYS_FSL_PBL_PBI board/varisys/cyrus/pbi.cfg
29 #if defined(CONFIG_ARCH_P5020)
30 #define CONFIG_SYS_CLK_FREQ 133000000
31 #define CONFIG_SYS_FSL_PBL_RCW board/varisys/cyrus/rcw_p5020_v2.cfg
32 #elif defined(CONFIG_ARCH_P5040)
33 #define CONFIG_SYS_CLK_FREQ 100000000
34 #define CONFIG_SYS_FSL_PBL_RCW board/varisys/cyrus/rcw_p5040.cfg
37 /* High Level Configuration Options */
38 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
40 #define CONFIG_SYS_MMC_MAX_DEVICE 1
42 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
43 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
44 #define CONFIG_PCIE1 /* PCIE controller 1 */
45 #define CONFIG_PCIE2 /* PCIE controller 2 */
46 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
47 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
49 #define CONFIG_ENV_OVERWRITE
51 #if defined(CONFIG_SDCARD)
52 #define CONFIG_SYS_EXTRA_ENV_RELOC
53 #define CONFIG_FSL_FIXED_MMC_LOCATION
54 #define CONFIG_SYS_MMC_ENV_DEV 0
55 #define CONFIG_ENV_SIZE 0x2000
56 #define CONFIG_ENV_OFFSET (512 * 1658)
60 * These can be toggled for performance analysis, otherwise use default.
62 #define CONFIG_SYS_CACHE_STASHING
63 #define CONFIG_BACKSIDE_L2_CACHE
64 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
65 #define CONFIG_BTB /* toggle branch predition */
66 #define CONFIG_DDR_ECC
68 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
69 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
72 #define CONFIG_ENABLE_36BIT_PHYS
74 #ifdef CONFIG_PHYS_64BIT
75 #define CONFIG_ADDR_MAP
76 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
79 /* test POST memory test */
81 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
82 #define CONFIG_SYS_MEMTEST_END 0x00400000
85 * Config the L3 Cache as L3 SRAM
87 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
88 #ifdef CONFIG_PHYS_64BIT
89 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE)
91 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR
93 #define CONFIG_SYS_L3_SIZE (1024 << 10)
94 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
96 #ifdef CONFIG_PHYS_64BIT
97 #define CONFIG_SYS_DCSRBAR 0xf0000000
98 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
104 #define CONFIG_VERY_BIG_RAM
105 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
106 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
108 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
109 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
111 #define CONFIG_DDR_SPD
113 #define CONFIG_SYS_SPD_BUS_NUM 1
114 #define SPD_EEPROM_ADDRESS1 0x51
115 #define SPD_EEPROM_ADDRESS2 0x52
116 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
119 * Local Bus Definitions
122 #define CONFIG_SYS_LBC0_BASE 0xe0000000 /* Start of LBC Registers */
123 #ifdef CONFIG_PHYS_64BIT
124 #define CONFIG_SYS_LBC0_BASE_PHYS 0xfe0000000ull
126 #define CONFIG_SYS_LBC0_BASE_PHYS CONFIG_SYS_LBC0_BASE
129 #define CONFIG_SYS_LBC1_BASE 0xe1000000 /* Start of LBC Registers */
130 #ifdef CONFIG_PHYS_64BIT
131 #define CONFIG_SYS_LBC1_BASE_PHYS 0xfe1000000ull
133 #define CONFIG_SYS_LBC1_BASE_PHYS CONFIG_SYS_LBC1_BASE
136 /* Set the local bus clock 1/16 of platform clock */
137 #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_16 | LCRR_EADC_1)
139 #define CONFIG_SYS_BR0_PRELIM \
140 (BR_PHYS_ADDR(CONFIG_SYS_LBC0_BASE_PHYS) | BR_PS_16 | BR_V)
141 #define CONFIG_SYS_BR1_PRELIM \
142 (BR_PHYS_ADDR(CONFIG_SYS_LBC1_BASE_PHYS) | BR_PS_16 | BR_V)
144 #define CONFIG_SYS_OR0_PRELIM 0xfff00010
145 #define CONFIG_SYS_OR1_PRELIM 0xfff00010
147 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
149 #if defined(CONFIG_RAMBOOT_PBL)
150 #define CONFIG_SYS_RAMBOOT
153 #define CONFIG_MISC_INIT_R
155 #define CONFIG_HWCONFIG
157 /* define to use L1 as initial stack */
158 #define CONFIG_L1_INIT_RAM
159 #define CONFIG_SYS_INIT_RAM_LOCK
160 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
161 #ifdef CONFIG_PHYS_64BIT
162 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
163 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
164 /* The assembler doesn't like typecast */
165 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
166 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
167 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
169 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
170 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
171 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
173 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
175 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
176 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
178 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
179 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
181 /* Serial Port - controlled on board with jumper J8
185 #define CONFIG_SYS_NS16550_SERIAL
186 #define CONFIG_SYS_NS16550_REG_SIZE 1
187 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
189 #define CONFIG_SYS_BAUDRATE_TABLE \
190 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
192 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
193 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
194 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
195 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
198 #define CONFIG_SYS_I2C
199 #define CONFIG_SYS_I2C_FSL
200 #define CONFIG_I2C_MULTI_BUS
201 #define CONFIG_I2C_CMD_TREE
202 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed and slave address */
203 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
204 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
205 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed and slave address */
206 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
207 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
208 #define CONFIG_SYS_FSL_I2C3_SPEED 400000 /* I2C speed and slave address */
209 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
210 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
211 #define CONFIG_SYS_FSL_I2C4_SPEED 400000 /* I2C speed and slave address */
212 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
213 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
215 #define CONFIG_ID_EEPROM
216 #define CONFIG_SYS_I2C_EEPROM_NXID
217 #define CONFIG_SYS_EEPROM_BUS_NUM 0
218 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
219 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
221 #define CONFIG_SYS_I2C_GENERIC_MAC
222 #define CONFIG_SYS_I2C_MAC1_BUS 3
223 #define CONFIG_SYS_I2C_MAC1_CHIP_ADDR 0x57
224 #define CONFIG_SYS_I2C_MAC1_DATA_ADDR 0xf2
225 #define CONFIG_SYS_I2C_MAC2_BUS 0
226 #define CONFIG_SYS_I2C_MAC2_CHIP_ADDR 0x50
227 #define CONFIG_SYS_I2C_MAC2_DATA_ADDR 0xfa
229 #define CONFIG_RTC_MCP79411 1
230 #define CONFIG_SYS_RTC_BUS_NUM 3
231 #define CONFIG_SYS_I2C_RTC_ADDR 0x6f
234 * eSPI - Enhanced SPI
239 * Memory space is mapped 1-1, but I/O space must start from 0.
242 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
243 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
244 #ifdef CONFIG_PHYS_64BIT
245 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
246 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
248 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
249 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
251 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
252 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
253 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
254 #ifdef CONFIG_PHYS_64BIT
255 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
257 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
259 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
261 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
262 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
263 #ifdef CONFIG_PHYS_64BIT
264 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
265 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
267 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
268 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
270 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
271 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
272 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
273 #ifdef CONFIG_PHYS_64BIT
274 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
276 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000
278 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
280 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
281 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
282 #ifdef CONFIG_PHYS_64BIT
283 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
284 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
286 #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000
287 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000
289 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
290 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
291 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
292 #ifdef CONFIG_PHYS_64BIT
293 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
295 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000
297 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
299 /* controller 4, Base address 203000 */
300 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
301 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
302 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */
303 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
304 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
305 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
308 #define CONFIG_SYS_BMAN_NUM_PORTALS 10
309 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
310 #ifdef CONFIG_PHYS_64BIT
311 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
313 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
315 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
316 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
317 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
318 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
319 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
320 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
321 CONFIG_SYS_BMAN_CENA_SIZE)
322 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
323 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
324 #define CONFIG_SYS_QMAN_NUM_PORTALS 10
325 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
326 #ifdef CONFIG_PHYS_64BIT
327 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
329 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
331 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
332 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
333 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
334 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
335 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
336 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
337 CONFIG_SYS_QMAN_CENA_SIZE)
338 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
339 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
341 #define CONFIG_SYS_DPAA_FMAN
342 /* Default address of microcode for the Linux Fman driver */
344 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
345 * about 825KB (1650 blocks), Env is stored after the image, and the env size is
346 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
348 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
349 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
351 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
352 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
354 #ifdef CONFIG_SYS_DPAA_FMAN
355 #define CONFIG_FMAN_ENET
359 #define CONFIG_PCI_INDIRECT_BRIDGE
361 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
362 #endif /* CONFIG_PCI */
365 #ifdef CONFIG_FSL_SATA_V2
366 #define CONFIG_SYS_SATA_MAX_DEVICE 2
368 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
369 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
371 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
372 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
377 #ifdef CONFIG_FMAN_ENET
378 #define CONFIG_SYS_TBIPA_VALUE 8
379 #define CONFIG_MII /* MII PHY management */
380 #define CONFIG_ETHPRIME "FM1@DTSEC4"
386 #define CONFIG_LOADS_ECHO /* echo on for serial download */
387 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
392 #define CONFIG_HAS_FSL_DR_USB
393 #define CONFIG_HAS_FSL_MPH_USB
395 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
396 #define CONFIG_USB_EHCI_FSL
397 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
398 #define CONFIG_EHCI_IS_TDI
399 /* _VIA_CONTROL_EP */
403 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
404 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
408 * Miscellaneous configurable options
410 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
413 * For booting Linux, the board info and command line data
414 * have to be in the first 64 MB of memory, since this is
415 * the maximum mapped by the Linux kernel during initialization.
417 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
418 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
420 #ifdef CONFIG_CMD_KGDB
421 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
425 * Environment Configuration
427 #define CONFIG_ROOTPATH "/opt/nfsroot"
428 #define CONFIG_BOOTFILE "uImage"
429 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
431 /* default location for tftp and bootm */
432 #define CONFIG_LOADADDR 1000000
434 #define __USB_PHY_TYPE utmi
436 #define CONFIG_EXTRA_ENV_SETTINGS \
437 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
438 "bank_intlv=cs0_cs1;" \
439 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
440 "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
442 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
443 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
444 "consoledev=ttyS0\0" \
445 "ramdiskaddr=2000000\0" \
446 "fdtaddr=1e00000\0" \
449 #define CONFIG_HDBOOT \
450 "setenv bootargs root=/dev/$bdev rw " \
451 "console=$consoledev,$baudrate $othbootargs;" \
452 "tftp $loadaddr $bootfile;" \
453 "tftp $fdtaddr $fdtfile;" \
454 "bootm $loadaddr - $fdtaddr"
456 #define CONFIG_NFSBOOTCOMMAND \
457 "setenv bootargs root=/dev/nfs rw " \
458 "nfsroot=$serverip:$rootpath " \
459 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
460 "console=$consoledev,$baudrate $othbootargs;" \
461 "tftp $loadaddr $bootfile;" \
462 "tftp $fdtaddr $fdtfile;" \
463 "bootm $loadaddr - $fdtaddr"
465 #define CONFIG_RAMBOOTCOMMAND \
466 "setenv bootargs root=/dev/ram rw " \
467 "console=$consoledev,$baudrate $othbootargs;" \
468 "tftp $ramdiskaddr $ramdiskfile;" \
469 "tftp $loadaddr $bootfile;" \
470 "tftp $fdtaddr $fdtfile;" \
471 "bootm $loadaddr $ramdiskaddr $fdtaddr"
473 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
475 #include <asm/fsl_secure_boot.h>
477 #endif /* __CONFIG_H */