2 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
4 * Based on davinci_dvevm.h. Original Copyrights follow:
6 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
29 #define CONFIG_DRIVER_TI_EMAC
30 /* check if direct NOR boot config is used */
31 #ifndef CONFIG_DIRECT_NOR_BOOT
32 #define CONFIG_USE_SPIFLASH
39 #define CONFIG_MACH_DAVINCI_DA850_EVM
40 #define CONFIG_ARM926EJS /* arm926ejs CPU core */
41 #define CONFIG_SOC_DA8XX /* TI DA8xx SoC */
42 #define CONFIG_SOC_DA850 /* TI DA850 SoC */
43 #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
44 #define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
45 #define CONFIG_SYS_OSCIN_FREQ 24000000
46 #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
47 #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
48 #define CONFIG_SYS_HZ 1000
49 #define CONFIG_SYS_DA850_PLL_INIT
50 #define CONFIG_SYS_DA850_DDR_INIT
52 #ifdef CONFIG_DIRECT_NOR_BOOT
53 #define CONFIG_ARCH_CPU_INIT
54 #define CONFIG_DA8XX_GPIO
55 #define CONFIG_SYS_TEXT_BASE 0x60000000
56 #define CONFIG_SYS_DV_NOR_BOOT_CFG (0x11)
57 #define CONFIG_DA850_LOWLEVEL
59 #define CONFIG_SYS_TEXT_BASE 0xc1080000
65 #define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */
66 #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
67 #define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */
68 #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
70 /* memtest start addr */
71 #define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000)
73 /* memtest will be run on 16MB */
74 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024)
76 #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
77 #define CONFIG_STACKSIZE (256*1024) /* regular stack */
79 #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \
80 DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \
81 DAVINCI_SYSCFG_SUSPSRC_SPI1 | \
82 DAVINCI_SYSCFG_SUSPSRC_UART2 | \
83 DAVINCI_SYSCFG_SUSPSRC_EMAC | \
84 DAVINCI_SYSCFG_SUSPSRC_I2C)
89 #define CONFIG_SYS_DV_CLKMODE 0
90 #define CONFIG_SYS_DA850_PLL0_POSTDIV 1
91 #define CONFIG_SYS_DA850_PLL0_PLLDIV1 0x8000
92 #define CONFIG_SYS_DA850_PLL0_PLLDIV2 0x8001
93 #define CONFIG_SYS_DA850_PLL0_PLLDIV3 0x8002
94 #define CONFIG_SYS_DA850_PLL0_PLLDIV4 0x8003
95 #define CONFIG_SYS_DA850_PLL0_PLLDIV5 0x8002
96 #define CONFIG_SYS_DA850_PLL0_PLLDIV6 CONFIG_SYS_DA850_PLL0_PLLDIV1
97 #define CONFIG_SYS_DA850_PLL0_PLLDIV7 0x8005
99 #define CONFIG_SYS_DA850_PLL1_POSTDIV 1
100 #define CONFIG_SYS_DA850_PLL1_PLLDIV1 0x8000
101 #define CONFIG_SYS_DA850_PLL1_PLLDIV2 0x8001
102 #define CONFIG_SYS_DA850_PLL1_PLLDIV3 0x8002
104 #define CONFIG_SYS_DA850_PLL0_PLLM 24
105 #define CONFIG_SYS_DA850_PLL1_PLLM 21
108 * DDR2 memory configuration
110 #define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
111 DV_DDR_PHY_EXT_STRBEN | \
112 (0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT))
114 #define CONFIG_SYS_DA850_DDR2_SDBCR ( \
115 (1 << DV_DDR_SDCR_MSDRAMEN_SHIFT) | \
116 (1 << DV_DDR_SDCR_DDREN_SHIFT) | \
117 (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \
118 (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \
119 (0x3 << DV_DDR_SDCR_CL_SHIFT) | \
120 (0x2 << DV_DDR_SDCR_IBANK_SHIFT) | \
121 (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
123 /* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
124 #define CONFIG_SYS_DA850_DDR2_SDBCR2 0
126 #define CONFIG_SYS_DA850_DDR2_SDTIMR ( \
127 (14 << DV_DDR_SDTMR1_RFC_SHIFT) | \
128 (2 << DV_DDR_SDTMR1_RP_SHIFT) | \
129 (2 << DV_DDR_SDTMR1_RCD_SHIFT) | \
130 (1 << DV_DDR_SDTMR1_WR_SHIFT) | \
131 (5 << DV_DDR_SDTMR1_RAS_SHIFT) | \
132 (8 << DV_DDR_SDTMR1_RC_SHIFT) | \
133 (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \
134 (0 << DV_DDR_SDTMR1_WTR_SHIFT))
136 #define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \
137 (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \
138 (0 << DV_DDR_SDTMR2_XP_SHIFT) | \
139 (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \
140 (17 << DV_DDR_SDTMR2_XSNR_SHIFT) | \
141 (199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \
142 (0 << DV_DDR_SDTMR2_RTP_SHIFT) | \
143 (0 << DV_DDR_SDTMR2_CKE_SHIFT))
145 #define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000494
146 #define CONFIG_SYS_DA850_DDR2_PBBPR 0x30
151 #define CONFIG_SYS_NS16550
152 #define CONFIG_SYS_NS16550_SERIAL
153 #define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */
154 #define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */
155 #define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
156 #define CONFIG_CONS_INDEX 1 /* use UART0 for console */
157 #define CONFIG_BAUDRATE 115200 /* Default baud rate */
160 #define CONFIG_SPI_FLASH
161 #define CONFIG_SPI_FLASH_STMICRO
162 #define CONFIG_SPI_FLASH_WINBOND
163 #define CONFIG_DAVINCI_SPI
164 #define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE
165 #define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID)
166 #define CONFIG_SF_DEFAULT_SPEED 30000000
167 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
169 #ifdef CONFIG_USE_SPIFLASH
170 #define CONFIG_SPL_SPI_SUPPORT
171 #define CONFIG_SPL_SPI_FLASH_SUPPORT
172 #define CONFIG_SPL_SPI_LOAD
173 #define CONFIG_SPL_SPI_BUS 0
174 #define CONFIG_SPL_SPI_CS 0
175 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000
176 #define CONFIG_SYS_SPI_U_BOOT_SIZE 0x30000
182 #define CONFIG_HARD_I2C
183 #define CONFIG_DRIVER_DAVINCI_I2C
184 #define CONFIG_SYS_I2C_SPEED 25000
185 #define CONFIG_SYS_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
186 #define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20
189 * Flash & Environment
191 #ifdef CONFIG_USE_NAND
192 #undef CONFIG_ENV_IS_IN_FLASH
193 #define CONFIG_NAND_DAVINCI
194 #define CONFIG_SYS_NO_FLASH
195 #define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */
196 #define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
197 #define CONFIG_ENV_SIZE (128 << 10)
198 #define CONFIG_SYS_NAND_USE_FLASH_BBT
199 #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
200 #define CONFIG_SYS_NAND_PAGE_2K
201 #define CONFIG_SYS_NAND_CS 3
202 #define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
203 #define CONFIG_SYS_CLE_MASK 0x10
204 #define CONFIG_SYS_ALE_MASK 0x8
205 #undef CONFIG_SYS_NAND_HW_ECC
206 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
207 #define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
208 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
209 #define CONFIG_SYS_NAND_PAGE_SIZE (2 << 10)
210 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10)
211 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x28000
212 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x60000
213 #define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000
214 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
215 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \
216 CONFIG_SYS_NAND_U_BOOT_SIZE - \
217 CONFIG_SYS_MALLOC_LEN - \
218 GENERATED_GBL_DATA_SIZE)
219 #define CONFIG_SYS_NAND_ECCPOS { \
220 24, 25, 26, 27, 28, \
221 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, \
222 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \
223 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \
225 #define CONFIG_SYS_NAND_PAGE_COUNT 64
226 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
227 #define CONFIG_SYS_NAND_ECCSIZE 512
228 #define CONFIG_SYS_NAND_ECCBYTES 10
229 #define CONFIG_SYS_NAND_OOBSIZE 64
230 #define CONFIG_SPL_NAND_SUPPORT
231 #define CONFIG_SPL_NAND_SIMPLE
232 #define CONFIG_SPL_NAND_LOAD
236 * Network & Ethernet Configuration
238 #ifdef CONFIG_DRIVER_TI_EMAC
240 #define CONFIG_BOOTP_DEFAULT
241 #define CONFIG_BOOTP_DNS
242 #define CONFIG_BOOTP_DNS2
243 #define CONFIG_BOOTP_SEND_HOSTNAME
244 #define CONFIG_NET_RETRY_COUNT 10
247 #ifdef CONFIG_USE_NOR
248 #define CONFIG_ENV_IS_IN_FLASH
249 #define CONFIG_FLASH_CFI_DRIVER
250 #define CONFIG_SYS_FLASH_CFI
251 #define CONFIG_SYS_FLASH_PROTECTION
252 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */
253 #define CONFIG_SYS_FLASH_SECT_SZ (128 << 10) /* 128KB */
254 #define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_SECT_SZ * 3)
255 #define CONFIG_ENV_SIZE (10 << 10) /* 10KB */
256 #define CONFIG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
257 #define PHYS_FLASH_SIZE (8 << 20) /* Flash size 8MB */
258 #define CONFIG_SYS_MAX_FLASH_SECT ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)\
260 #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ
263 #ifdef CONFIG_USE_SPIFLASH
264 #undef CONFIG_ENV_IS_IN_FLASH
265 #undef CONFIG_ENV_IS_IN_NAND
266 #define CONFIG_ENV_IS_IN_SPI_FLASH
267 #define CONFIG_ENV_SIZE (64 << 10)
268 #define CONFIG_ENV_OFFSET (256 << 10)
269 #define CONFIG_ENV_SECT_SIZE (64 << 10)
270 #define CONFIG_SYS_NO_FLASH
274 * U-Boot general configuration
276 #define CONFIG_MISC_INIT_R
277 #define CONFIG_BOARD_EARLY_INIT_F
278 #define CONFIG_BOOTFILE "uImage" /* Boot file name */
279 #define CONFIG_SYS_PROMPT "U-Boot > " /* Command Prompt */
280 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
281 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
282 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
283 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
284 #define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000)
285 #define CONFIG_VERSION_VARIABLE
286 #define CONFIG_AUTO_COMPLETE
287 #define CONFIG_SYS_HUSH_PARSER
288 #define CONFIG_CMDLINE_EDITING
289 #define CONFIG_SYS_LONGHELP
290 #define CONFIG_CRC32_VERIFY
291 #define CONFIG_MX_CYCLIC
296 #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
297 #define CONFIG_HWCONFIG /* enable hwconfig */
298 #define CONFIG_CMDLINE_TAG
299 #define CONFIG_REVISION_TAG
300 #define CONFIG_SETUP_MEMORY_TAGS
301 #define CONFIG_BOOTARGS \
302 "mem=32M console=ttyS2,115200n8 root=/dev/mtdblock2 rw noinitrd ip=dhcp"
303 #define CONFIG_BOOTDELAY 3
304 #define CONFIG_EXTRA_ENV_SETTINGS "hwconfig=dsp:wake=yes"
309 #include <config_cmd_default.h>
310 #define CONFIG_CMD_ENV
311 #define CONFIG_CMD_ASKENV
312 #define CONFIG_CMD_DHCP
313 #define CONFIG_CMD_DIAG
314 #define CONFIG_CMD_MII
315 #define CONFIG_CMD_PING
316 #define CONFIG_CMD_SAVES
317 #define CONFIG_CMD_MEMORY
319 #ifdef CONFIG_CMD_BDI
320 #define CONFIG_CLOCKS
323 #ifndef CONFIG_DRIVER_TI_EMAC
324 #undef CONFIG_CMD_NET
325 #undef CONFIG_CMD_DHCP
326 #undef CONFIG_CMD_MII
327 #undef CONFIG_CMD_PING
330 #ifdef CONFIG_USE_NAND
331 #undef CONFIG_CMD_FLASH
332 #undef CONFIG_CMD_IMLS
333 #define CONFIG_CMD_NAND
335 #define CONFIG_CMD_MTDPARTS
336 #define CONFIG_MTD_DEVICE
337 #define CONFIG_MTD_PARTITIONS
339 #define CONFIG_RBTREE
340 #define CONFIG_CMD_UBI
341 #define CONFIG_CMD_UBIFS
344 #ifdef CONFIG_USE_SPIFLASH
345 #undef CONFIG_CMD_IMLS
346 #undef CONFIG_CMD_FLASH
347 #define CONFIG_CMD_SPI
348 #define CONFIG_CMD_SF
349 #define CONFIG_CMD_SAVEENV
352 #if !defined(CONFIG_USE_NAND) && \
353 !defined(CONFIG_USE_NOR) && \
354 !defined(CONFIG_USE_SPIFLASH)
355 #define CONFIG_ENV_IS_NOWHERE
356 #define CONFIG_SYS_NO_FLASH
357 #define CONFIG_ENV_SIZE (16 << 10)
358 #undef CONFIG_CMD_IMLS
359 #undef CONFIG_CMD_ENV
362 /* SD/MMC configuration */
363 #ifndef CONFIG_USE_NOR
365 #define CONFIG_DAVINCI_MMC_SD1
366 #define CONFIG_GENERIC_MMC
367 #define CONFIG_DAVINCI_MMC
371 * Enable MMC commands only when
372 * MMC support is present
375 #define CONFIG_DOS_PARTITION
376 #define CONFIG_CMD_EXT2
377 #define CONFIG_CMD_FAT
378 #define CONFIG_CMD_MMC
381 #ifndef CONFIG_DIRECT_NOR_BOOT
382 /* defines for SPL */
384 #define CONFIG_SPL_SERIAL_SUPPORT
385 #define CONFIG_SPL_LIBCOMMON_SUPPORT
386 #define CONFIG_SPL_LIBGENERIC_SUPPORT
387 #define CONFIG_SPL_LDSCRIPT "board/$(BOARDDIR)/u-boot-spl-da850evm.lds"
388 #define CONFIG_SPL_STACK 0x8001ff00
389 #define CONFIG_SPL_TEXT_BASE 0x80000000
390 #define CONFIG_SPL_MAX_SIZE 32768
393 /* Load U-Boot Image From MMC */
394 #ifdef CONFIG_SPL_MMC_LOAD
395 #define CONFIG_SPL_MMC_SUPPORT
396 #define CONFIG_SPL_FAT_SUPPORT
397 #define CONFIG_SPL_LIBDISK_SUPPORT
398 #define CONFIG_SYS_MMC_U_BOOT_OFFS 0x75
399 #define CONFIG_SYS_MMC_U_BOOT_SIZE 0x30000
400 #undef CONFIG_SPL_SPI_LOAD
403 /* additions for new relocation code, must added to all boards */
404 #define CONFIG_SYS_SDRAM_BASE 0xc0000000
406 #ifdef CONFIG_DIRECT_NOR_BOOT
407 #define CONFIG_SYS_INIT_SP_ADDR 0x8001ff00
409 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
410 GENERATED_GBL_DATA_SIZE)
411 #endif /* CONFIG_DIRECT_NOR_BOOT */
412 #endif /* __CONFIG_H */