2 * Copyright (C) 2009 Texas Instruments Incorporated
4 * SPDX-License-Identifier: GPL-2.0+
10 #define DAVINCI_DM355LEOPARD
12 #define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 3rd stage loader */
13 #define CONFIG_SYS_NO_FLASH /* that is, no *NOR* flash */
14 #define CONFIG_SYS_CONSOLE_INFO_QUIET
16 /* SoC Configuration */
17 #define CONFIG_ARM926EJS /* arm926ejs CPU */
18 #define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
19 #define CONFIG_SYS_HZ_CLOCK 24000000 /* timer0 freq */
20 #define CONFIG_SOC_DM355 /* DM355 based board */
23 #define CONFIG_NR_DRAM_BANKS 1
24 #define PHYS_SDRAM_1 0x80000000
25 #define PHYS_SDRAM_1_SIZE (128 << 20) /* 128 MiB */
27 /* Serial Driver info: UART0 for console */
28 #define CONFIG_SYS_NS16550
29 #define CONFIG_SYS_NS16550_SERIAL
30 #define CONFIG_SYS_NS16550_REG_SIZE -4
31 #define CONFIG_SYS_NS16550_COM1 0x01c20000
32 #define CONFIG_SYS_NS16550_CLK CONFIG_SYS_HZ_CLOCK
33 #define CONFIG_CONS_INDEX 1
34 #define CONFIG_BAUDRATE 115200
36 /* Ethernet: external DM9000 */
37 #define CONFIG_DRIVER_DM9000 1
38 #define CONFIG_DM9000_BASE 0x04000000
39 #define DM9000_IO CONFIG_DM9000_BASE
40 #define DM9000_DATA (CONFIG_DM9000_BASE + 16)
43 #define CONFIG_SYS_I2C
44 #define CONFIG_SYS_I2C_DAVINCI
45 #define CONFIG_SYS_DAVINCI_I2C_SPEED 400000
46 #define CONFIG_SYS_DAVINCI_I2C_SLAVE 0x10
49 #define CONFIG_NAND_DAVINCI
50 #define CONFIG_SYS_NAND_CS 2
51 #define CONFIG_SYS_NAND_USE_FLASH_BBT
52 #define CONFIG_SYS_NAND_HW_ECC
54 #define CONFIG_SYS_NAND_BASE_LIST { 0x02000000, }
55 #define CONFIG_SYS_MAX_NAND_DEVICE 1
57 /* U-Boot command configuration */
58 #include <config_cmd_default.h>
61 #undef CONFIG_CMD_FLASH
62 #undef CONFIG_CMD_FPGA
63 #undef CONFIG_CMD_SETGETDCR
65 #define CONFIG_CMD_ASKENV
66 #define CONFIG_CMD_DHCP
67 #define CONFIG_CMD_I2C
68 #define CONFIG_CMD_PING
69 #define CONFIG_CMD_SAVES
75 #ifdef CONFIG_NAND_DAVINCI
76 #define CONFIG_CMD_MTDPARTS
77 #define CONFIG_MTD_PARTITIONS
78 #define CONFIG_MTD_DEVICE
79 #define CONFIG_CMD_NAND
80 #define CONFIG_CMD_UBI
84 #define CONFIG_CRC32_VERIFY
85 #define CONFIG_MX_CYCLIC
87 /* U-Boot general configuration */
88 #define CONFIG_BOOTFILE "uImage" /* Boot file name */
89 #define CONFIG_SYS_PROMPT "DM355 LEOPARD # "
90 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
91 #define CONFIG_SYS_PBSIZE /* Print buffer size */ \
92 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
93 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
94 #define CONFIG_SYS_HUSH_PARSER
95 #define CONFIG_SYS_LONGHELP
97 #ifdef CONFIG_NAND_DAVINCI
98 #define CONFIG_ENV_SIZE (256 << 10) /* 256 KiB */
99 #define CONFIG_ENV_IS_IN_NAND
100 #define CONFIG_ENV_OFFSET 0x3C0000
101 #undef CONFIG_ENV_IS_IN_FLASH
102 #define CONFIG_ENV_OVERWRITE
105 #define CONFIG_BOOTDELAY 3
106 #define CONFIG_BOOTCOMMAND "dhcp;bootm"
107 #define CONFIG_BOOTARGS \
108 "console=ttyS0,115200n8 " \
109 "root=/dev/mmcblk0p1 rootwait rootfstype=ext3 ro"
111 #define CONFIG_CMDLINE_EDITING
112 #define CONFIG_VERSION_VARIABLE
113 #define CONFIG_TIMESTAMP
115 #define CONFIG_NET_RETRY_COUNT 10
117 /* U-Boot memory configuration */
118 #define CONFIG_SYS_MALLOC_LEN (1 << 20) /* 1 MiB */
119 #define CONFIG_SYS_MEMTEST_START 0x87000000 /* physical address */
120 #define CONFIG_SYS_MEMTEST_END 0x88000000 /* test 16MB RAM */
122 /* Linux interfacing */
123 #define CONFIG_CMDLINE_TAG
124 #define CONFIG_SETUP_MEMORY_TAGS
125 #define CONFIG_SYS_BARGSIZE 1024 /* bootarg Size */
126 #define CONFIG_SYS_LOAD_ADDR 0x80700000 /* kernel address */
128 #define MTDIDS_DEFAULT "nand0=davinci_nand.0"
130 #ifdef CONFIG_SYS_NAND_LARGEPAGE
131 #define PART_BOOT "2m(bootloader)ro,"
133 /* Assume 16K erase blocks; allow a few bad ones. */
134 #define PART_BOOT "512k(bootloader)ro,"
137 #define PART_KERNEL "4m(kernel)," /* kernel + initramfs */
138 #define PART_REST "-(filesystem)"
140 #define MTDPARTS_DEFAULT \
141 "mtdparts=davinci_nand.0:" PART_BOOT PART_KERNEL PART_REST
143 #define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MB */
145 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
146 #define CONFIG_SYS_INIT_SP_ADDR \
147 (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
149 #endif /* __CONFIG_H */