2 * Copyright (C) 2014-2015 Stefan Roese <sr@denx.de>
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef _CONFIG_DB_MV7846MP_GP_H
8 #define _CONFIG_DB_MV7846MP_GP_H
11 * High Level Configuration Options (easy to change)
13 #define CONFIG_DB_784MP_GP /* Board target name for DDR training */
16 * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
17 * for DDR ECC byte filling in the SPL before loading the main
20 #define CONFIG_SYS_TCLK 250000000 /* 250MHz */
23 #define CONFIG_SYS_I2C
24 #define CONFIG_SYS_I2C_MVTWSI
25 #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
26 #define CONFIG_SYS_I2C_SLAVE 0x0
27 #define CONFIG_SYS_I2C_SPEED 100000
29 /* USB/EHCI configuration */
30 #define CONFIG_EHCI_IS_TDI
31 #define CONFIG_USB_MAX_CONTROLLER_COUNT 3
33 /* SPI NOR flash default params, used by sf commands */
34 #define CONFIG_SF_DEFAULT_SPEED 1000000
35 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
37 /* Environment in SPI NOR flash */
38 #define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */
39 #define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */
40 #define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */
42 #define CONFIG_PHY_MARVELL /* there is a marvell phy */
43 #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
46 #define CONFIG_SYS_SATA_MAX_DEVICE 2
50 #ifndef CONFIG_SPL_BUILD
51 #define CONFIG_PCI_MVEBU
52 #define CONFIG_PCI_SCAN_SHOW
56 #define CONFIG_SYS_NAND_USE_FLASH_BBT
57 #define CONFIG_SYS_NAND_ONFI_DETECTION
60 * mv-common.h should be defined after CMD configs since it used them
61 * to enable certain macros
63 #include "mv-common.h"
66 * Memory layout while starting into the bin_hdr via the
69 * 0x4000.4000 - 0x4003.4000 headers space (192KiB)
70 * 0x4000.4030 bin_hdr start address
71 * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB)
72 * 0x4007.fffc BootROM stack top
74 * The address space between 0x4007.fffc and 0x400f.fff is not locked in
75 * L2 cache thus cannot be used.
80 #define CONFIG_SPL_TEXT_BASE 0x40004030
81 #define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030)
83 #define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10))
84 #define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
86 #ifdef CONFIG_SPL_BUILD
87 #define CONFIG_SYS_MALLOC_SIMPLE
90 #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
91 #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
93 /* SPL related SPI defines */
94 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
95 #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
97 /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
98 #define CONFIG_SPD_EEPROM 0x4e
99 #define CONFIG_BOARD_ECC_SUPPORT /* this board supports ECC */
101 #endif /* _CONFIG_DB_MV7846MP_GP_H */