3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
9 * This file contains the configuration parameters for the dbau1x00 board.
15 #define CONFIG_DBAU1X00 1
16 #define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */
18 #define CONFIG_DISPLAY_BOARDINFO
20 #ifdef CONFIG_DBAU1000
21 /* Also known as Merlot */
22 #define CONFIG_SOC_AU1000 1
24 #ifdef CONFIG_DBAU1100
25 #define CONFIG_SOC_AU1100 1
27 #ifdef CONFIG_DBAU1500
28 #define CONFIG_SOC_AU1500 1
30 #ifdef CONFIG_DBAU1550
32 #define CONFIG_SOC_AU1550 1
34 #error "No valid board set"
40 #define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */
42 #define CONFIG_BAUDRATE 115200
46 #define CONFIG_TIMESTAMP /* Print image info with timestamp */
47 #undef CONFIG_BOOTARGS
49 #define CONFIG_EXTRA_ENV_SETTINGS \
50 "addmisc=setenv bootargs ${bootargs} " \
51 "console=ttyS0,${baudrate} " \
53 "bootfile=/tftpboot/vmlinux.srec\0" \
54 "load=tftp 80500000 ${u-boot}\0" \
57 #ifdef CONFIG_DBAU1550
58 /* Boot from flash by default, revert to bootp */
59 #define CONFIG_BOOTCOMMAND "bootm 0xbfc20000; bootp; bootm"
60 #else /* CONFIG_DBAU1550 */
61 #define CONFIG_BOOTCOMMAND "bootp;bootm"
62 #endif /* CONFIG_DBAU1550 */
68 #define CONFIG_BOOTP_BOOTFILESIZE
69 #define CONFIG_BOOTP_BOOTPATH
70 #define CONFIG_BOOTP_GATEWAY
71 #define CONFIG_BOOTP_HOSTNAME
75 * Command line configuration.
77 #undef CONFIG_CMD_BEDBUG
82 #ifdef CONFIG_DBAU1550
86 #undef CONFIG_CMD_PCMCIA
90 #define CONFIG_CMD_IDE
91 #define CONFIG_CMD_DHCP
97 * Miscellaneous configurable options
99 #define CONFIG_SYS_LONGHELP /* undef to save memory */
101 #define CONFIG_SYS_PROMPT "DbAu1xx0 # " /* Monitor Command Prompt */
103 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
104 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
105 #define CONFIG_SYS_MAXARGS 16 /* max number of command args*/
107 #define CONFIG_SYS_MALLOC_LEN 128*1024
109 #define CONFIG_SYS_BOOTPARAMS_LEN 128*1024
111 #define CONFIG_SYS_MHZ 396
113 #if (CONFIG_SYS_MHZ % 12) != 0
114 #error "Invalid CPU frequency - must be multiple of 12!"
117 #define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
119 #define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */
121 #define CONFIG_SYS_LOAD_ADDR 0x81000000 /* default load address */
123 #define CONFIG_SYS_MEMTEST_START 0x80100000
124 #define CONFIG_SYS_MEMTEST_END 0x80800000
126 /*-----------------------------------------------------------------------
127 * FLASH and environment organization
129 #ifdef CONFIG_DBAU1550
131 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
132 #define CONFIG_SYS_MAX_FLASH_SECT (512) /* max number of sectors on one chip */
134 #define PHYS_FLASH_1 0xb8000000 /* Flash Bank #1 */
135 #define PHYS_FLASH_2 0xbc000000 /* Flash Bank #2 */
137 #else /* CONFIG_DBAU1550 */
139 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
140 #define CONFIG_SYS_MAX_FLASH_SECT (128) /* max number of sectors on one chip */
142 #define PHYS_FLASH_1 0xbec00000 /* Flash Bank #1 */
143 #define PHYS_FLASH_2 0xbfc00000 /* Flash Bank #2 */
145 #endif /* CONFIG_DBAU1550 */
147 #define CONFIG_SYS_FLASH_BANKS_LIST {PHYS_FLASH_1, PHYS_FLASH_2}
149 #define CONFIG_SYS_FLASH_CFI 1
150 #define CONFIG_FLASH_CFI_DRIVER 1
152 /* The following #defines are needed to get flash environment right */
153 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
154 #define CONFIG_SYS_MONITOR_LEN (192 << 10)
156 #define CONFIG_SYS_INIT_SP_OFFSET 0x400000
158 /* We boot from this flash, selected with dip switch */
159 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_2
161 /* timeout values are in ticks */
162 #define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */
163 #define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Write */
165 #define CONFIG_ENV_IS_NOWHERE 1
167 /* Address and size of Primary Environment Sector */
168 #define CONFIG_ENV_ADDR 0xB0030000
169 #define CONFIG_ENV_SIZE 0x10000
171 #define CONFIG_FLASH_16BIT
173 #define CONFIG_NR_DRAM_BANKS 2
176 #ifdef CONFIG_DBAU1550
182 #define CONFIG_MEMSIZE_IN_BYTES
184 #ifndef CONFIG_DBAU1550
185 /*---ATA PCMCIA ------------------------------------*/
186 #define CONFIG_SYS_PCMCIA_MEM_SIZE 0x4000000 /* Offset to slot 1 FIXME!!! */
187 #define CONFIG_SYS_PCMCIA_MEM_ADDR 0x20000000
188 #define CONFIG_PCMCIA_SLOT_A
190 #define CONFIG_ATAPI 1
191 #define CONFIG_MAC_PARTITION 1
193 /* We run CF in "true ide" mode or a harddrive via pcmcia */
194 #define CONFIG_IDE_PCMCIA 1
196 /* We only support one slot for now */
197 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
198 #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
200 #undef CONFIG_IDE_LED /* LED for ide not supported */
201 #undef CONFIG_IDE_RESET /* reset for ide not supported */
203 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
205 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
207 /* Offset for data I/O */
208 #define CONFIG_SYS_ATA_DATA_OFFSET 8
210 /* Offset for normal register accesses */
211 #define CONFIG_SYS_ATA_REG_OFFSET 0
213 /* Offset for alternate registers */
214 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
215 #endif /* CONFIG_DBAU1550 */
217 /*-----------------------------------------------------------------------
218 * Cache Configuration
220 #define CONFIG_SYS_DCACHE_SIZE 16384
221 #define CONFIG_SYS_ICACHE_SIZE 16384
222 #define CONFIG_SYS_CACHELINE_SIZE 32
224 #endif /* __CONFIG_H */