3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
9 * This file contains the configuration parameters for the dbau1x00 board.
15 #define CONFIG_DBAU1X00 1
16 #define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */
18 #define CONFIG_SYS_GENERIC_BOARD
19 #define CONFIG_DISPLAY_BOARDINFO
21 #ifdef CONFIG_DBAU1000
22 /* Also known as Merlot */
23 #define CONFIG_SOC_AU1000 1
25 #ifdef CONFIG_DBAU1100
26 #define CONFIG_SOC_AU1100 1
28 #ifdef CONFIG_DBAU1500
29 #define CONFIG_SOC_AU1500 1
31 #ifdef CONFIG_DBAU1550
33 #define CONFIG_SOC_AU1550 1
35 #error "No valid board set"
41 #define CONFIG_ETHADDR DE:AD:BE:EF:01:01 /* Ethernet address */
43 #define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */
45 #define CONFIG_BAUDRATE 115200
49 #define CONFIG_TIMESTAMP /* Print image info with timestamp */
50 #undef CONFIG_BOOTARGS
52 #define CONFIG_EXTRA_ENV_SETTINGS \
53 "addmisc=setenv bootargs ${bootargs} " \
54 "console=ttyS0,${baudrate} " \
56 "bootfile=/tftpboot/vmlinux.srec\0" \
57 "load=tftp 80500000 ${u-boot}\0" \
60 #ifdef CONFIG_DBAU1550
61 /* Boot from flash by default, revert to bootp */
62 #define CONFIG_BOOTCOMMAND "bootm 0xbfc20000; bootp; bootm"
63 #else /* CONFIG_DBAU1550 */
64 #define CONFIG_BOOTCOMMAND "bootp;bootm"
65 #endif /* CONFIG_DBAU1550 */
71 #define CONFIG_BOOTP_BOOTFILESIZE
72 #define CONFIG_BOOTP_BOOTPATH
73 #define CONFIG_BOOTP_GATEWAY
74 #define CONFIG_BOOTP_HOSTNAME
78 * Command line configuration.
80 #include <config_cmd_default.h>
83 #undef CONFIG_CMD_BEDBUG
85 #undef CONFIG_CMD_SAVEENV
87 #undef CONFIG_CMD_FPGA
92 #ifdef CONFIG_DBAU1550
94 #define CONFIG_CMD_FLASH
95 #define CONFIG_CMD_LOADB
96 #define CONFIG_CMD_NET
100 #undef CONFIG_CMD_NFS
101 #undef CONFIG_CMD_PCMCIA
105 #define CONFIG_CMD_IDE
106 #define CONFIG_CMD_DHCP
108 #undef CONFIG_CMD_FLASH
109 #undef CONFIG_CMD_LOADB
110 #undef CONFIG_CMD_LOADS
116 * Miscellaneous configurable options
118 #define CONFIG_SYS_LONGHELP /* undef to save memory */
120 #define CONFIG_SYS_PROMPT "DbAu1xx0 # " /* Monitor Command Prompt */
122 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
123 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
124 #define CONFIG_SYS_MAXARGS 16 /* max number of command args*/
126 #define CONFIG_SYS_MALLOC_LEN 128*1024
128 #define CONFIG_SYS_BOOTPARAMS_LEN 128*1024
130 #define CONFIG_SYS_MHZ 396
132 #if (CONFIG_SYS_MHZ % 12) != 0
133 #error "Invalid CPU frequency - must be multiple of 12!"
136 #define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
138 #define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */
140 #define CONFIG_SYS_LOAD_ADDR 0x81000000 /* default load address */
142 #define CONFIG_SYS_MEMTEST_START 0x80100000
143 #define CONFIG_SYS_MEMTEST_END 0x80800000
145 /*-----------------------------------------------------------------------
146 * FLASH and environment organization
148 #ifdef CONFIG_DBAU1550
150 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
151 #define CONFIG_SYS_MAX_FLASH_SECT (512) /* max number of sectors on one chip */
153 #define PHYS_FLASH_1 0xb8000000 /* Flash Bank #1 */
154 #define PHYS_FLASH_2 0xbc000000 /* Flash Bank #2 */
156 #else /* CONFIG_DBAU1550 */
158 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
159 #define CONFIG_SYS_MAX_FLASH_SECT (128) /* max number of sectors on one chip */
161 #define PHYS_FLASH_1 0xbec00000 /* Flash Bank #1 */
162 #define PHYS_FLASH_2 0xbfc00000 /* Flash Bank #2 */
164 #endif /* CONFIG_DBAU1550 */
166 #define CONFIG_SYS_FLASH_BANKS_LIST {PHYS_FLASH_1, PHYS_FLASH_2}
168 #define CONFIG_SYS_FLASH_CFI 1
169 #define CONFIG_FLASH_CFI_DRIVER 1
171 /* The following #defines are needed to get flash environment right */
172 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
173 #define CONFIG_SYS_MONITOR_LEN (192 << 10)
175 #define CONFIG_SYS_INIT_SP_OFFSET 0x400000
177 /* We boot from this flash, selected with dip switch */
178 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_2
180 /* timeout values are in ticks */
181 #define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */
182 #define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Write */
184 #define CONFIG_ENV_IS_NOWHERE 1
186 /* Address and size of Primary Environment Sector */
187 #define CONFIG_ENV_ADDR 0xB0030000
188 #define CONFIG_ENV_SIZE 0x10000
190 #define CONFIG_FLASH_16BIT
192 #define CONFIG_NR_DRAM_BANKS 2
195 #ifdef CONFIG_DBAU1550
201 #define CONFIG_MEMSIZE_IN_BYTES
203 #ifndef CONFIG_DBAU1550
204 /*---ATA PCMCIA ------------------------------------*/
205 #define CONFIG_SYS_PCMCIA_MEM_SIZE 0x4000000 /* Offset to slot 1 FIXME!!! */
206 #define CONFIG_SYS_PCMCIA_MEM_ADDR 0x20000000
207 #define CONFIG_PCMCIA_SLOT_A
209 #define CONFIG_ATAPI 1
210 #define CONFIG_MAC_PARTITION 1
212 /* We run CF in "true ide" mode or a harddrive via pcmcia */
213 #define CONFIG_IDE_PCMCIA 1
215 /* We only support one slot for now */
216 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
217 #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
219 #undef CONFIG_IDE_LED /* LED for ide not supported */
220 #undef CONFIG_IDE_RESET /* reset for ide not supported */
222 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
224 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
226 /* Offset for data I/O */
227 #define CONFIG_SYS_ATA_DATA_OFFSET 8
229 /* Offset for normal register accesses */
230 #define CONFIG_SYS_ATA_REG_OFFSET 0
232 /* Offset for alternate registers */
233 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
234 #endif /* CONFIG_DBAU1550 */
236 /*-----------------------------------------------------------------------
237 * Cache Configuration
239 #define CONFIG_SYS_DCACHE_SIZE 16384
240 #define CONFIG_SYS_ICACHE_SIZE 16384
241 #define CONFIG_SYS_CACHELINE_SIZE 32
243 #endif /* __CONFIG_H */