3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
9 * This file contains the configuration parameters for the dbau1x00 board.
15 #define CONFIG_DBAU1X00 1
16 #define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */
18 #define CONFIG_DISPLAY_BOARDINFO
20 #ifdef CONFIG_DBAU1000
21 /* Also known as Merlot */
22 #define CONFIG_SOC_AU1000 1
24 #ifdef CONFIG_DBAU1100
25 #define CONFIG_SOC_AU1100 1
27 #ifdef CONFIG_DBAU1500
28 #define CONFIG_SOC_AU1500 1
30 #ifdef CONFIG_DBAU1550
32 #define CONFIG_SOC_AU1550 1
34 #error "No valid board set"
40 #define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */
42 #define CONFIG_BAUDRATE 115200
46 #define CONFIG_TIMESTAMP /* Print image info with timestamp */
47 #undef CONFIG_BOOTARGS
49 #define CONFIG_EXTRA_ENV_SETTINGS \
50 "addmisc=setenv bootargs ${bootargs} " \
51 "console=ttyS0,${baudrate} " \
53 "bootfile=/tftpboot/vmlinux.srec\0" \
54 "load=tftp 80500000 ${u-boot}\0" \
57 #ifdef CONFIG_DBAU1550
58 /* Boot from flash by default, revert to bootp */
59 #define CONFIG_BOOTCOMMAND "bootm 0xbfc20000; bootp; bootm"
60 #else /* CONFIG_DBAU1550 */
61 #define CONFIG_BOOTCOMMAND "bootp;bootm"
62 #endif /* CONFIG_DBAU1550 */
68 #define CONFIG_BOOTP_BOOTFILESIZE
69 #define CONFIG_BOOTP_BOOTPATH
70 #define CONFIG_BOOTP_GATEWAY
71 #define CONFIG_BOOTP_HOSTNAME
75 * Command line configuration.
77 #include <config_cmd_default.h>
80 #undef CONFIG_CMD_BEDBUG
82 #undef CONFIG_CMD_SAVEENV
84 #undef CONFIG_CMD_FPGA
89 #ifdef CONFIG_DBAU1550
91 #define CONFIG_CMD_FLASH
92 #define CONFIG_CMD_LOADB
97 #undef CONFIG_CMD_PCMCIA
101 #define CONFIG_CMD_IDE
102 #define CONFIG_CMD_DHCP
104 #undef CONFIG_CMD_FLASH
105 #undef CONFIG_CMD_LOADB
106 #undef CONFIG_CMD_LOADS
112 * Miscellaneous configurable options
114 #define CONFIG_SYS_LONGHELP /* undef to save memory */
116 #define CONFIG_SYS_PROMPT "DbAu1xx0 # " /* Monitor Command Prompt */
118 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
119 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
120 #define CONFIG_SYS_MAXARGS 16 /* max number of command args*/
122 #define CONFIG_SYS_MALLOC_LEN 128*1024
124 #define CONFIG_SYS_BOOTPARAMS_LEN 128*1024
126 #define CONFIG_SYS_MHZ 396
128 #if (CONFIG_SYS_MHZ % 12) != 0
129 #error "Invalid CPU frequency - must be multiple of 12!"
132 #define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
134 #define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */
136 #define CONFIG_SYS_LOAD_ADDR 0x81000000 /* default load address */
138 #define CONFIG_SYS_MEMTEST_START 0x80100000
139 #define CONFIG_SYS_MEMTEST_END 0x80800000
141 /*-----------------------------------------------------------------------
142 * FLASH and environment organization
144 #ifdef CONFIG_DBAU1550
146 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
147 #define CONFIG_SYS_MAX_FLASH_SECT (512) /* max number of sectors on one chip */
149 #define PHYS_FLASH_1 0xb8000000 /* Flash Bank #1 */
150 #define PHYS_FLASH_2 0xbc000000 /* Flash Bank #2 */
152 #else /* CONFIG_DBAU1550 */
154 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
155 #define CONFIG_SYS_MAX_FLASH_SECT (128) /* max number of sectors on one chip */
157 #define PHYS_FLASH_1 0xbec00000 /* Flash Bank #1 */
158 #define PHYS_FLASH_2 0xbfc00000 /* Flash Bank #2 */
160 #endif /* CONFIG_DBAU1550 */
162 #define CONFIG_SYS_FLASH_BANKS_LIST {PHYS_FLASH_1, PHYS_FLASH_2}
164 #define CONFIG_SYS_FLASH_CFI 1
165 #define CONFIG_FLASH_CFI_DRIVER 1
167 /* The following #defines are needed to get flash environment right */
168 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
169 #define CONFIG_SYS_MONITOR_LEN (192 << 10)
171 #define CONFIG_SYS_INIT_SP_OFFSET 0x400000
173 /* We boot from this flash, selected with dip switch */
174 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_2
176 /* timeout values are in ticks */
177 #define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */
178 #define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Write */
180 #define CONFIG_ENV_IS_NOWHERE 1
182 /* Address and size of Primary Environment Sector */
183 #define CONFIG_ENV_ADDR 0xB0030000
184 #define CONFIG_ENV_SIZE 0x10000
186 #define CONFIG_FLASH_16BIT
188 #define CONFIG_NR_DRAM_BANKS 2
191 #ifdef CONFIG_DBAU1550
197 #define CONFIG_MEMSIZE_IN_BYTES
199 #ifndef CONFIG_DBAU1550
200 /*---ATA PCMCIA ------------------------------------*/
201 #define CONFIG_SYS_PCMCIA_MEM_SIZE 0x4000000 /* Offset to slot 1 FIXME!!! */
202 #define CONFIG_SYS_PCMCIA_MEM_ADDR 0x20000000
203 #define CONFIG_PCMCIA_SLOT_A
205 #define CONFIG_ATAPI 1
206 #define CONFIG_MAC_PARTITION 1
208 /* We run CF in "true ide" mode or a harddrive via pcmcia */
209 #define CONFIG_IDE_PCMCIA 1
211 /* We only support one slot for now */
212 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
213 #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
215 #undef CONFIG_IDE_LED /* LED for ide not supported */
216 #undef CONFIG_IDE_RESET /* reset for ide not supported */
218 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
220 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
222 /* Offset for data I/O */
223 #define CONFIG_SYS_ATA_DATA_OFFSET 8
225 /* Offset for normal register accesses */
226 #define CONFIG_SYS_ATA_REG_OFFSET 0
228 /* Offset for alternate registers */
229 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
230 #endif /* CONFIG_DBAU1550 */
232 /*-----------------------------------------------------------------------
233 * Cache Configuration
235 #define CONFIG_SYS_DCACHE_SIZE 16384
236 #define CONFIG_SYS_ICACHE_SIZE 16384
237 #define CONFIG_SYS_CACHELINE_SIZE 32
239 #endif /* __CONFIG_H */