3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
9 * This file contains the configuration parameters for the dbau1x00 board.
15 #define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */
17 #ifdef CONFIG_DBAU1000
18 /* Also known as Merlot */
19 #define CONFIG_SOC_AU1000 1
21 #ifdef CONFIG_DBAU1100
22 #define CONFIG_SOC_AU1100 1
24 #ifdef CONFIG_DBAU1500
25 #define CONFIG_SOC_AU1500 1
27 #ifdef CONFIG_DBAU1550
29 #define CONFIG_SOC_AU1550 1
31 #error "No valid board set"
39 #define CONFIG_TIMESTAMP /* Print image info with timestamp */
41 #define CONFIG_EXTRA_ENV_SETTINGS \
42 "addmisc=setenv bootargs ${bootargs} " \
43 "console=ttyS0,${baudrate} " \
45 "bootfile=/tftpboot/vmlinux.srec\0" \
46 "load=tftp 80500000 ${u-boot}\0" \
49 #ifdef CONFIG_DBAU1550
50 /* Boot from flash by default, revert to bootp */
51 #define CONFIG_BOOTCOMMAND "bootm 0xbfc20000; bootp; bootm"
52 #else /* CONFIG_DBAU1550 */
53 #define CONFIG_BOOTCOMMAND "bootp;bootm"
54 #endif /* CONFIG_DBAU1550 */
59 #define CONFIG_BOOTP_BOOTFILESIZE
62 * Command line configuration.
66 * Miscellaneous configurable options
69 #define CONFIG_SYS_MALLOC_LEN 128*1024
71 #define CONFIG_SYS_BOOTPARAMS_LEN 128*1024
73 #define CONFIG_SYS_MHZ 396
75 #if (CONFIG_SYS_MHZ % 12) != 0
76 #error "Invalid CPU frequency - must be multiple of 12!"
79 #define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
81 #define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */
83 #define CONFIG_SYS_LOAD_ADDR 0x81000000 /* default load address */
85 #define CONFIG_SYS_MEMTEST_START 0x80100000
86 #define CONFIG_SYS_MEMTEST_END 0x80800000
88 /*-----------------------------------------------------------------------
89 * FLASH and environment organization
91 #ifdef CONFIG_DBAU1550
93 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
94 #define CONFIG_SYS_MAX_FLASH_SECT (512) /* max number of sectors on one chip */
96 #define PHYS_FLASH_1 0xb8000000 /* Flash Bank #1 */
97 #define PHYS_FLASH_2 0xbc000000 /* Flash Bank #2 */
99 #else /* CONFIG_DBAU1550 */
101 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
102 #define CONFIG_SYS_MAX_FLASH_SECT (128) /* max number of sectors on one chip */
104 #define PHYS_FLASH_1 0xbec00000 /* Flash Bank #1 */
105 #define PHYS_FLASH_2 0xbfc00000 /* Flash Bank #2 */
107 #endif /* CONFIG_DBAU1550 */
109 #define CONFIG_SYS_FLASH_BANKS_LIST {PHYS_FLASH_1, PHYS_FLASH_2}
111 #define CONFIG_SYS_FLASH_CFI 1
112 #define CONFIG_FLASH_CFI_DRIVER 1
114 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
115 #define CONFIG_SYS_MONITOR_LEN (192 << 10)
117 #define CONFIG_SYS_INIT_SP_OFFSET 0x400000
119 /* We boot from this flash, selected with dip switch */
120 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_2
122 /* timeout values are in ticks */
123 #define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */
124 #define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Write */
126 /* Address and size of Primary Environment Sector */
127 #define CONFIG_ENV_ADDR 0xB0030000
128 #define CONFIG_ENV_SIZE 0x10000
130 #define CONFIG_FLASH_16BIT
132 #define CONFIG_NR_DRAM_BANKS 2
134 #ifdef CONFIG_DBAU1550
140 #define CONFIG_MEMSIZE_IN_BYTES
142 #ifndef CONFIG_DBAU1550
143 /*---ATA PCMCIA ------------------------------------*/
144 #define CONFIG_SYS_PCMCIA_MEM_SIZE 0x4000000 /* Offset to slot 1 FIXME!!! */
145 #define CONFIG_SYS_PCMCIA_MEM_ADDR 0x20000000
146 #define CONFIG_PCMCIA_SLOT_A
148 #define CONFIG_ATAPI 1
150 /* We run CF in "true ide" mode or a harddrive via pcmcia */
151 #define CONFIG_IDE_PCMCIA 1
153 /* We only support one slot for now */
154 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
155 #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
157 #undef CONFIG_IDE_RESET /* reset for ide not supported */
159 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
161 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
163 /* Offset for data I/O */
164 #define CONFIG_SYS_ATA_DATA_OFFSET 8
166 /* Offset for normal register accesses */
167 #define CONFIG_SYS_ATA_REG_OFFSET 0
169 /* Offset for alternate registers */
170 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
171 #endif /* CONFIG_DBAU1550 */
173 #endif /* __CONFIG_H */