2 * (C) Copyright 2006-2008
4 * Richard Woodruff <r-woodruff2@ti.com>
5 * Syed Mohammed Khasim <x0khasim@ti.com>
8 * Frederik Kriewitz <frederik@kriewitz.eu>
10 * Configuration settings for the DevKit8000 board.
12 * SPDX-License-Identifier: GPL-2.0+
18 /* High Level Configuration Options */
19 #define CONFIG_MACH_TYPE MACH_TYPE_DEVKIT8000
22 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
23 * 64 bytes before this address should be set aside for u-boot.img's
24 * header. That is 0x800FFFC0--0x80100000 should not be used for any
27 #define CONFIG_SYS_TEXT_BASE 0x80100000
29 #define CONFIG_SPL_BSS_START_ADDR 0x80000500 /* leave space for bootargs*/
30 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
32 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000
33 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */
37 /* Physical Memory Map */
38 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
40 #include <configs/ti_omap3_common.h>
42 #define CONFIG_MISC_INIT_R
44 #define CONFIG_REVISION_TAG 1
46 /* Size of malloc() pool */
47 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
49 #undef CONFIG_SYS_MALLOC_LEN
50 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
52 /* Hardware drivers */
54 #define CONFIG_NET_RETRY_COUNT 20
55 #define CONFIG_DRIVER_DM9000 1
56 #define CONFIG_DM9000_BASE 0x2c000000
57 #define DM9000_IO CONFIG_DM9000_BASE
58 #define DM9000_DATA (CONFIG_DM9000_BASE + 0x400)
59 #define CONFIG_DM9000_USE_16BIT 1
60 #define CONFIG_DM9000_NO_SROM 1
61 #undef CONFIG_DM9000_DEBUG
65 #undef CONFIG_OMAP3_SPI
68 #undef CONFIG_SYS_I2C_OMAP24XX
69 #define CONFIG_SYS_I2C_OMAP34XX
72 #define CONFIG_TWL4030_LED 1
75 #define MTDIDS_DEFAULT "nand0=nand"
76 #define MTDPARTS_DEFAULT "mtdparts=nand:" \
83 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
85 #define CONFIG_JFFS2_NAND
86 /* nand device jffs2 lives on */
87 #define CONFIG_JFFS2_DEV "nand0"
88 /* start of jffs2 partition */
89 #define CONFIG_JFFS2_PART_OFFSET 0x680000
90 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */
93 /* commands to include */
94 #define CONFIG_CMD_JFFS2 /* JFFS2 Support */
95 #define CONFIG_CMD_NAND_LOCK_UNLOCK /* nand (un)lock commands */
97 #undef CONFIG_SUPPORT_RAW_INITRD
98 #undef CONFIG_FAT_WRITE
100 /* BOOTP/DHCP options */
101 #define CONFIG_BOOTP_SUBNETMASK
102 #define CONFIG_BOOTP_GATEWAY
103 #define CONFIG_BOOTP_HOSTNAME
104 #define CONFIG_BOOTP_NISDOMAIN
105 #define CONFIG_BOOTP_BOOTPATH
106 #define CONFIG_BOOTP_BOOTFILESIZE
107 #define CONFIG_BOOTP_DNS
108 #define CONFIG_BOOTP_DNS2
109 #define CONFIG_BOOTP_SEND_HOSTNAME
110 #define CONFIG_BOOTP_NTPSERVER
111 #define CONFIG_BOOTP_TIMEOFFSET
112 #undef CONFIG_BOOTP_VENDOREX
114 /* Environment information */
115 #define CONFIG_EXTRA_ENV_SETTINGS \
116 "loadaddr=0x82000000\0" \
117 "console=ttyO2,115200n8\0" \
120 "dvimode=1024x768MR-16@60\0" \
121 "defaultdisplay=dvi\0" \
122 "nfsopts=hard,tcp,rsize=65536,wsize=65536\0" \
125 "setenv bootargs console=${console} " \
127 "omapfb.mode=dvi:${dvimode} " \
128 "omapdss.def_disp=${defaultdisplay}\0" \
131 "setenv bootargs ${bootargs} " \
132 "root=/dev/mmcblk0p2 " \
137 "setenv bootargs ${bootargs} " \
138 "omapfb.mode=dvi:${dvimode} " \
139 "omapdss.def_disp=${defaultdisplay} " \
140 "root=/dev/mtdblock4 " \
141 "rootfstype=jffs2 " \
145 "setenv bootargs ${bootargs} " \
147 "nfsroot=${serverip}:${rootpath},${nfsopts} " \
148 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off " \
151 "dnsip2=${dnsip2}\0" \
152 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
153 "bootscript=echo Running bootscript from mmc ...; " \
154 "source ${loadaddr}\0" \
155 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
156 "eraseenv=nand unlock 0x260000 0x20000; nand erase 0x260000 0x20000\0" \
157 "mmcboot=echo Booting from mmc ...; " \
159 "bootm ${loadaddr}\0" \
160 "nandboot=echo Booting from nand ...; " \
162 "nand read ${loadaddr} 280000 400000; " \
163 "bootm ${loadaddr}\0" \
164 "netboot=echo Booting from network ...; " \
165 "dhcp ${loadaddr}; " \
167 "bootm ${loadaddr}\0" \
168 "autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \
169 "if run loadbootscript; then " \
172 "if run loaduimage; then " \
174 "else run nandboot; " \
177 "else run nandboot; fi\0"
179 #define CONFIG_BOOTCOMMAND "run autoboot"
181 /* Boot Argument Buffer Size */
182 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x07000000)
183 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
184 0x01000000) /* 16MB */
186 /* NAND and environment organization */
187 #define CONFIG_ENV_IS_IN_NAND 1
188 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
190 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
193 #define CONFIG_SYS_SRAM_START 0x40200000
194 #define CONFIG_SYS_SRAM_SIZE 0x10000
196 /* Defines for SPL */
198 #undef CONFIG_SPL_TEXT_BASE
199 #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/
201 /* NAND boot config */
202 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT
203 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
204 #define CONFIG_SYS_NAND_PAGE_COUNT 64
205 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
206 #define CONFIG_SYS_NAND_OOBSIZE 64
207 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
208 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
209 #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
212 #define CONFIG_SYS_NAND_ECCSIZE 512
213 #define CONFIG_SYS_NAND_ECCBYTES 3
214 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
216 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
217 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x200000
219 /* SPL OS boot options */
220 #define CONFIG_CMD_SPL_WRITE_SIZE 0x400 /* 1024 byte */
221 #define CONFIG_CMD_SPL_NAND_OFS (CONFIG_SYS_NAND_SPL_KERNEL_OFFS+\
223 #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000
225 #undef CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR
226 #undef CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR
227 #undef CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS
228 #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x500 /* address 0xa0000 */
229 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x8 /* address 0x1000 */
230 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 8 /* 4KB */
232 #undef CONFIG_SYS_SPL_ARGS_ADDR
233 #define CONFIG_SYS_SPL_ARGS_ADDR (PHYS_SDRAM_1 + 0x100)
235 #endif /* __CONFIG_H */