2 * (C) Copyright 2006-2008
4 * Richard Woodruff <r-woodruff2@ti.com>
5 * Syed Mohammed Khasim <x0khasim@ti.com>
8 * Frederik Kriewitz <frederik@kriewitz.eu>
10 * Configuration settings for the DevKit8000 board.
12 * See file CREDITS for list of people who contributed to this
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
34 /* High Level Configuration Options */
35 #define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */
36 #define CONFIG_OMAP 1 /* in a TI OMAP core */
37 #define CONFIG_OMAP34XX 1 /* which is a 34XX */
38 #define CONFIG_OMAP3430 1 /* which is in a 3430 */
39 #define CONFIG_OMAP3_DEVKIT8000 1 /* working with DevKit8000 */
41 #define CONFIG_SDRC /* The chip has SDRC controller */
43 #include <asm/arch/cpu.h> /* get chip and board defs */
44 #include <asm/arch/omap3.h>
46 /* Display CPU and Board information */
47 #define CONFIG_DISPLAY_CPUINFO 1
48 #define CONFIG_DISPLAY_BOARDINFO 1
51 #define V_OSCK 26000000 /* Clock output from T2 */
52 #define V_SCLK (V_OSCK >> 1)
54 #undef CONFIG_USE_IRQ /* no support for IRQs */
55 #define CONFIG_MISC_INIT_R
57 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
58 #define CONFIG_SETUP_MEMORY_TAGS 1
59 #define CONFIG_INITRD_TAG 1
60 #define CONFIG_REVISION_TAG 1
62 /* Size of malloc() pool */
63 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
65 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
68 /* Hardware drivers */
70 /* DDR - I use Micron DDR */
71 #define CONFIG_OMAP3_MICRON_DDR 1
74 #define CONFIG_NET_MULTI 1
75 #define CONFIG_NET_RETRY_COUNT 20
76 #define CONFIG_DRIVER_DM9000 1
77 #define CONFIG_DM9000_BASE 0x2c000000
78 #define DM9000_IO CONFIG_DM9000_BASE
79 #define DM9000_DATA (CONFIG_DM9000_BASE + 0x400)
80 #define CONFIG_DM9000_USE_16BIT 1
81 #define CONFIG_DM9000_NO_SROM 1
82 #undef CONFIG_DM9000_DEBUG
84 /* NS16550 Configuration */
85 #define CONFIG_SYS_NS16550
86 #define CONFIG_SYS_NS16550_SERIAL
87 #define CONFIG_SYS_NS16550_REG_SIZE (-4)
88 #define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
90 /* select serial console configuration */
91 #define CONFIG_CONS_INDEX 3
92 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
93 #define CONFIG_SERIAL3 3
94 #define CONFIG_BAUDRATE 115200
95 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
100 #define CONFIG_OMAP3_MMC 1
101 #define CONFIG_DOS_PARTITION 1
104 #define CONFIG_HARD_I2C 1
105 #define CONFIG_SYS_I2C_SPEED 100000
106 #define CONFIG_SYS_I2C_SLAVE 1
107 #define CONFIG_SYS_I2C_BUS 0
108 #define CONFIG_SYS_I2C_BUS_SELECT 1
109 #define CONFIG_DRIVER_OMAP34XX_I2C 1
112 #define CONFIG_TWL4030_POWER 1
113 #define CONFIG_TWL4030_LED 1
115 /* Board NAND Info */
116 #define CONFIG_SYS_NO_FLASH /* no NOR flash */
117 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
118 #define MTDIDS_DEFAULT "nand0=nand"
119 #define MTDPARTS_DEFAULT "mtdparts=nand:" \
122 "128k(u-boot-env)," \
126 #define CONFIG_NAND_OMAP_GPMC
127 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
129 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
130 /* to access nand at */
132 #define GPMC_NAND_ECC_LP_x16_LAYOUT 1
134 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
136 #define CONFIG_JFFS2_NAND
137 /* nand device jffs2 lives on */
138 #define CONFIG_JFFS2_DEV "nand0"
139 /* start of jffs2 partition */
140 #define CONFIG_JFFS2_PART_OFFSET 0x680000
141 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */
144 /* commands to include */
145 #include <config_cmd_default.h>
147 #define CONFIG_CMD_DHCP /* DHCP support */
148 #define CONFIG_CMD_EXT2 /* EXT2 Support */
149 #define CONFIG_CMD_FAT /* FAT support */
150 #define CONFIG_CMD_I2C /* I2C serial bus support */
151 #define CONFIG_CMD_JFFS2 /* JFFS2 Support */
152 #define CONFIG_CMD_MMC /* MMC support */
153 #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
154 #define CONFIG_CMD_NAND /* NAND support */
155 #define CONFIG_CMD_NAND_LOCK_UNLOCK /* nand (un)lock commands */
157 #undef CONFIG_CMD_FPGA /* FPGA configuration Support */
158 #undef CONFIG_CMD_IMI /* iminfo */
160 /* BOOTP/DHCP options */
161 #define CONFIG_BOOTP_SUBNETMASK
162 #define CONFIG_BOOTP_GATEWAY
163 #define CONFIG_BOOTP_HOSTNAME
164 #define CONFIG_BOOTP_NISDOMAIN
165 #define CONFIG_BOOTP_BOOTPATH
166 #define CONFIG_BOOTP_BOOTFILESIZE
167 #define CONFIG_BOOTP_DNS
168 #define CONFIG_BOOTP_DNS2
169 #define CONFIG_BOOTP_SEND_HOSTNAME
170 #define CONFIG_BOOTP_NTPSERVER
171 #define CONFIG_BOOTP_TIMEOFFSET
172 #undef CONFIG_BOOTP_VENDOREX
174 /* Environment information */
175 #define CONFIG_ENV_OVERWRITE /* allow to overwrite serial and ethaddr */
177 #define CONFIG_BOOTDELAY 3
179 #define CONFIG_EXTRA_ENV_SETTINGS \
180 "loadaddr=0x82000000\0" \
181 "console=ttyS2,115200n8\0" \
183 "dvimode=1024x768MR-16@60\0" \
184 "defaultdisplay=dvi\0" \
185 "nfsopts=hard,tcp,rsize=65536,wsize=65536\0" \
188 "setenv bootargs console=${console} " \
190 "omapfb.mode=dvi:${dvimode} " \
191 "omapdss.def_disp=${defaultdisplay}\0" \
194 "setenv bootargs ${bootargs} " \
195 "root=/dev/mmcblk0p2 " \
199 "setenv bootargs ${bootargs} " \
200 "omapfb.mode=dvi:${dvimode} " \
201 "omapdss.def_disp=${defaultdisplay} " \
202 "root=/dev/mtdblock4 " \
203 "rootfstype=jffs2 " \
207 "setenv bootargs ${bootargs} " \
209 "nfsroot=${serverip}:${rootpath},${nfsopts} " \
210 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off " \
213 "dnsip2=${dnsip2}\0" \
214 "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
215 "bootscript=echo Running bootscript from mmc ...; " \
216 "source ${loadaddr}\0" \
217 "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
218 "eraseenv=nand unlock 0x260000 0x20000; nand erase 0x260000 0x20000\0" \
219 "mmcboot=echo Booting from mmc ...; " \
221 "bootm ${loadaddr}\0" \
222 "nandboot=echo Booting from nand ...; " \
224 "nand read ${loadaddr} 280000 400000; " \
225 "bootm ${loadaddr}\0" \
226 "netboot=echo Booting from network ...; " \
227 "dhcp ${loadaddr}; " \
229 "bootm ${loadaddr}\0" \
230 "autoboot=if mmc init 0; then " \
231 "if run loadbootscript; then " \
234 "if run loaduimage; then " \
236 "else run nandboot; " \
239 "else run nandboot; fi\0"
242 #define CONFIG_BOOTCOMMAND "run autoboot"
244 /* Miscellaneous configurable options */
245 #define CONFIG_SYS_LONGHELP /* undef to save memory */
246 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
247 #define CONFIG_AUTO_COMPLETE 1
248 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
249 #define CONFIG_SYS_PROMPT "OMAP3 DevKit8000 # "
250 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
251 /* Print Buffer Size */
252 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
253 sizeof(CONFIG_SYS_PROMPT) + 16)
254 #define CONFIG_SYS_MAXARGS 128 /* max number of command args */
256 /* Boot Argument Buffer Size */
257 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
259 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x07000000)
260 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
261 0x01000000) /* 16MB */
263 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0 + 0x02000000)
266 * OMAP3 has 12 GP timers, they can be driven by the system clock
267 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
268 * This rate is divided by a local divisor.
270 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
271 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
272 #define CONFIG_SYS_HZ 1000
274 /* The stack sizes are set up in start.S using the settings below */
275 #define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
276 #ifdef CONFIG_USE_IRQ
277 #define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */
278 #define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */
281 /* Physical Memory Map */
282 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
283 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
284 #define PHYS_SDRAM_1_SIZE (128 << 20) /* at least 128 MiB */
285 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
287 /* SDRAM Bank Allocation method */
290 /* NAND and environment organization */
291 #define PISMO1_NAND_SIZE GPMC_SIZE_128M
293 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
295 #define CONFIG_ENV_IS_IN_NAND 1
296 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
298 #define CONFIG_ENV_OFFSET boot_flash_off
301 extern unsigned int boot_flash_base;
302 extern volatile unsigned int boot_flash_env_addr;
303 extern unsigned int boot_flash_off;
304 extern unsigned int boot_flash_sec;
305 extern unsigned int boot_flash_type;
308 #endif /* __CONFIG_H */