2 * (C) Copyright 2003-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * (C) Copyright 2005-2007
6 * Modified for InterControl digsyMTC MPC5200 board by
7 * Frank Bodammer, GCD Hard- & Software GmbH,
8 * frank.bodammer@gcd-solutions.de
10 * (C) Copyright 2009 Semihalf
11 * Optimized for digsyMTC by: Grzegorz Bernacki <gjb@semihalf.com>
13 * SPDX-License-Identifier: GPL-2.0+
20 * High Level Configuration Options
23 #define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
24 #define CONFIG_DIGSY_MTC 1 /* ... on InterControl digsyMTC board */
27 * Valid values for CONFIG_SYS_TEXT_BASE are:
28 * 0xFFF00000 boot high (standard configuration)
30 * 0x00100000 boot from RAM (for testing only)
32 #ifndef CONFIG_SYS_TEXT_BASE
33 #define CONFIG_SYS_TEXT_BASE 0xFFF00000 /* Standard: boot high */
36 #define CONFIG_SYS_MPC5XXX_CLKIN 33000000
38 #define CONFIG_SYS_CACHELINE_SIZE 32
41 * Serial console configuration
43 #define CONFIG_PSC_CONSOLE 4 /* console is on PSC4 */
44 #define CONFIG_SYS_BAUDRATE_TABLE \
45 { 9600, 19200, 38400, 57600, 115200, 230400 }
49 * 0x40000000 - 0x4fffffff - PCI Memory
50 * 0x50000000 - 0x50ffffff - PCI IO Space
52 #define CONFIG_PCI_SCAN_SHOW 1
53 #define CONFIG_PCI_BOOTDELAY 250
55 #define CONFIG_PCI_MEM_BUS 0x40000000
56 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
57 #define CONFIG_PCI_MEM_SIZE 0x10000000
59 #define CONFIG_PCI_IO_BUS 0x50000000
60 #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
61 #define CONFIG_PCI_IO_SIZE 0x01000000
70 #define CONFIG_VIDEO_MB862xx
71 #define CONFIG_VIDEO_MB862xx_ACCEL
72 #define CONFIG_VIDEO_CORALP
73 #define CONFIG_VIDEO_LOGO
74 #define CONFIG_VIDEO_BMP_LOGO
75 #define CONFIG_SPLASH_SCREEN
76 #define CONFIG_VIDEO_BMP_GZIP
77 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) /* decompressed img */
79 /* Coral-PA clock frequency, geo and other both 133MHz */
80 #define CONFIG_SYS_MB862xx_CCF 0x00050000
81 /* Video SDRAM parameters */
82 #define CONFIG_SYS_MB862xx_MMR 0x11d7fa72
86 * Command line configuration.
88 #define CONFIG_CMD_IDE
89 #define CONFIG_CMD_IRQ
90 #define CONFIG_CMD_PCI
91 #define CONFIG_CMD_REGINFO
92 #define CONFIG_CMD_SAVES
94 #if (CONFIG_SYS_TEXT_BASE == 0xFF000000)
95 #define CONFIG_SYS_LOWBOOT 1
102 #undef CONFIG_BOOTARGS
104 #define CONFIG_EXTRA_ENV_SETTINGS \
105 "fw_image=digsyMPC.img\0" \
106 "mtcb_start=mtc led diag orange; run mtcb_1\0" \
107 "mtcb_clearled=for x in user1 user2 usbpwr usbbusy; " \
108 "do mtc led $x; done\0" \
109 "mtcb_1=if mtc key; then run mtcb_clearled mtcb_update; " \
110 "else run mtcb_fw; fi\0" \
111 "mtcb_fw=if bootm ff000000; then echo FIRMWARE OK!; " \
112 "else echo BAD FIRMWARE CRC!; mtc led diag red; fi\0" \
113 "mtcb_update=mtc led user1 orange;" \
114 "while mtc key; do ; done; run mtcb_2;\0" \
115 "mtcb_2=mtc led user1 green 2; usb reset; run mtcb_usb1;\0" \
116 "mtcb_usb1=if fatload usb 0 400000 script.img; " \
117 "then run mtcb_doscript; else run mtcb_usb2; fi\0" \
118 "mtcb_usb2=if fatload usb 0 400000 $fw_image; " \
119 "then run mtcb_dousb; else run mtcb_ide; fi\0" \
120 "mtcb_doscript=run mtcb_usbleds; mtc led user2 orange 2; " \
121 "run mtcb_wait_flickr mtcb_ds_1;\0" \
122 "mtcb_ds_1=if imi 400000; then mtc led usbbusy; " \
123 "source 400000; else run mtcb_error; fi\0" \
124 "mtcb_dousb=run mtcb_usbleds mtcb_wait_flickr mtcb_du_1;\0" \
125 "mtcb_du_1=if imi 400000; then run mtcb_du_2; " \
126 "else run mtcb_error; fi\0" \
127 "mtcb_du_2=run mtcb_clear mtcb_prog; mtc led usbbusy; " \
128 "run mtcb_checkfw\0" \
129 "mtcb_checkfw=if imi ff000000; then run mtcb_success; " \
130 "else run mtcb_error; fi\0" \
131 "mtcb_waitkey=mtc key; until test $? -eq 0; do mtc key; done\0" \
132 "mtcb_wait_flickr=run mtcb_waitkey mtcb_uledflckr\0" \
133 "mtcb_usbleds=mtc led usbpwr green; mtc led usbbusy orange 1;\0"\
134 "mtcb_uledflckr=mtc led user1 orange 11\0" \
135 "mtcb_error=mtc led user1 red\0" \
136 "mtcb_clear=erase ff000000 ff0fffff\0" \
137 "mtcb_prog=cp.b 400000 ff000000 ${filesize}\0" \
138 "mtcb_success=mtc led user1 green\0" \
139 "mtcb_ide=if fatload ide 0 400000 $fw_image;" \
140 "then run mtcb_doide; else run mtcb_error; fi\0" \
141 "mtcb_doide=mtc led user2 green 1;" \
142 "run mtcb_wait_flickr mtcb_di_1;\0" \
143 "mtcb_di_1=if imi 400000; then run mtcb_di_2;" \
144 "else run mtcb_error; fi\0" \
145 "mtcb_di_2=run mtcb_clear; run mtcb_prog mtcb_checkfw\0" \
146 "ramdisk_num_sector=16\0" \
147 "flash_base=ff000000\0" \
148 "flashdisk_size=e00000\0" \
149 "env_sector=fff60000\0" \
150 "flashdisk_start=ff100000\0" \
151 "load_cmd=tftp 400000 digsyMPC.img\0" \
152 "clear_cmd=erase ff000000 ff0fffff\0" \
153 "flash_cmd=cp.b 400000 ff000000 ${filesize}\0" \
154 "update_cmd=run load_cmd; " \
156 "run clear_cmd flash_cmd; " \
157 "iminfo ff000000\0" \
159 "spi_watchdog=no\0" \
161 "ftps_user1=admin\0" \
162 "ftps_pass1=admin\0" \
166 "plc_sio_baud=57600\0" \
167 "plc_sio_parity=no\0" \
170 "plc_eth_srv=yes\0" \
171 "plc_eth_port=1200\0" \
175 "plc_can1_routing=no\0" \
176 "plc_can1_baudrate=250\0" \
177 "plc_can2_routing=no\0" \
178 "plc_can2_baudrate=250\0" \
179 "plc_can3_routing=no\0" \
180 "plc_can3_baudrate=250\0" \
181 "plc_can4_routing=no\0" \
182 "plc_can4_baudrate=250\0" \
184 "console=ttyPSC0\0" \
185 "kernel_addr_r=400000\0" \
186 "fdt_addr_r=600000\0" \
187 "nfsargs=setenv bootargs root=/dev/nfs rw " \
188 "nfsroot=${serverip}:${rootpath}\0" \
189 "addip=setenv bootargs ${bootargs} " \
190 "ip=${ipaddr}:${serverip}:${gatewayip}:" \
191 "${netmask}:${hostname}:${netdev}:off panic=1\0" \
192 "addcons=setenv bootargs ${bootargs} console=${console},${baudrate}\0"\
193 "rootpath=/opt/eldk/ppc_6xx\0" \
194 "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
195 "tftp ${fdt_addr_r} ${fdt_file};" \
196 "run nfsargs addip addcons;" \
197 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
198 "load=tftp 200000 ${u-boot}\0" \
199 "update=protect off FFF00000 +${filesize};" \
200 "erase FFF00000 +${filesize};" \
201 "cp.b 200000 FFF00000 ${filesize};" \
202 "protect on FFF00000 +${filesize}\0" \
205 #define CONFIG_BOOTCOMMAND "run mtcb_start"
208 * Flash configuration
210 #define CONFIG_SYS_FLASH_CFI 1
211 #define CONFIG_FLASH_CFI_DRIVER 1
213 #if defined(CONFIG_DIGSY_REV5)
214 #define CONFIG_SYS_FLASH_BASE 0xFE000000
215 #define CONFIG_SYS_FLASH_BASE_CS1 0xFC000000
216 #define CONFIG_SYS_MAX_FLASH_BANKS 2
217 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \
218 CONFIG_SYS_FLASH_BASE_CS1}
219 #define CONFIG_SYS_UPDATE_FLASH_SIZE
220 #define CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
222 #define CONFIG_SYS_FLASH_BASE 0xFF000000
223 #define CONFIG_SYS_MAX_FLASH_BANKS 1
224 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
227 #define CONFIG_SYS_MAX_FLASH_SECT 256
228 #define CONFIG_FLASH_16BIT
229 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
230 #define CONFIG_SYS_FLASH_SIZE 0x01000000
231 #define CONFIG_SYS_FLASH_ERASE_TOUT 240000
232 #define CONFIG_SYS_FLASH_WRITE_TOUT 500
234 #define OF_CPU "PowerPC,5200@0"
235 #define OF_SOC "soc5200@f0000000"
236 #define OF_TBCLK (bd->bi_busfreq / 4)
238 #define CONFIG_BOARD_EARLY_INIT_R
239 #define CONFIG_MISC_INIT_R
242 * Environment settings
244 #define CONFIG_ENV_IS_IN_FLASH 1
245 #if defined(CONFIG_LOWBOOT)
246 #define CONFIG_ENV_ADDR 0xFF060000
247 #else /* CONFIG_LOWBOOT */
248 #define CONFIG_ENV_ADDR 0xFFF60000
249 #endif /* CONFIG_LOWBOOT */
250 #define CONFIG_ENV_SIZE 0x10000
251 #define CONFIG_ENV_SECT_SIZE 0x20000
252 #define CONFIG_ENV_OVERWRITE 1
257 #define CONFIG_SYS_MBAR 0xF0000000
258 #define CONFIG_SYS_SDRAM_BASE 0x00000000
259 #if !defined(CONFIG_SYS_LOWBOOT)
260 #define CONFIG_SYS_DEFAULT_MBAR 0x80000000
262 #define CONFIG_SYS_DEFAULT_MBAR 0xF0000000
266 * Use SRAM until RAM will be available
268 #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
269 #define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
271 #define CONFIG_SYS_GBL_DATA_OFFSET \
272 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
273 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
275 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
276 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
277 #define CONFIG_SYS_RAMBOOT 1
280 #define CONFIG_SYS_MONITOR_LEN (256 << 10)
281 #define CONFIG_SYS_MALLOC_LEN (4096 << 10)
282 #define CONFIG_SYS_BOOTMAPSZ (8 << 20)
285 * Ethernet configuration
287 #define CONFIG_MPC5xxx_FEC 1
288 #define CONFIG_MPC5xxx_FEC_MII100
289 #if defined(CONFIG_DIGSY_REV5)
290 #define CONFIG_PHY_ADDR 0x01
292 #define CONFIG_PHY_ADDR 0x00
294 #define CONFIG_PHY_RESET_DELAY 1000
296 #define CONFIG_NETCONSOLE /* include NetConsole support */
300 * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1)
301 * Bit 0 (mask 0x80000000) : 0x1
302 * SPI on Tmr2/3/4/5 pins
303 * Bit 2:3 (mask 0x30000000) : 0x2
304 * ATA cs0/1 on csb_4/5
305 * Bit 6:7 (mask 0x03000000) : 0x2
306 * Ethernet 100Mbit with MD
307 * Bits 12:15 (mask 0x000f0000): 0x5
309 * Bits 18:19 (mask 0x00003000) : 0x2
310 * PSC3 - USB2 on PSC3
311 * Bits 20:23 (mask 0x00000f00) : 0x1
312 * PSC2 - CAN1&2 on PSC2 pins
313 * Bits 25:27 (mask 0x00000070) : 0x1
314 * PSC1 - AC97 functionality
315 * Bits 29:31 (mask 0x00000007) : 0x2
317 #define CONFIG_SYS_GPS_PORT_CONFIG 0xA2552112
320 * Miscellaneous configurable options
322 #define CONFIG_SYS_LONGHELP
323 #define CONFIG_AUTO_COMPLETE 1
324 #define CONFIG_CMDLINE_EDITING 1
326 #define CONFIG_MX_CYCLIC 1
328 #define CONFIG_SYS_CBSIZE 1024
329 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
330 #define CONFIG_SYS_MAXARGS 32
331 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
333 #define CONFIG_SYS_ALT_MEMTEST
334 #define CONFIG_SYS_MEMTEST_SCRATCH 0x00001000
335 #define CONFIG_SYS_MEMTEST_START 0x00010000
336 #define CONFIG_SYS_MEMTEST_END 0x019fffff
338 #define CONFIG_SYS_LOAD_ADDR 0x00100000
341 * Various low-level settings
343 #define CONFIG_SYS_SDRAM_CS1 1
344 #define CONFIG_SYS_XLB_PIPELINING 1
346 #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
347 #define CONFIG_SYS_HID0_FINAL HID0_ICE
349 #if defined(CONFIG_SYS_LOWBOOT)
350 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
351 #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
352 #define CONFIG_SYS_BOOTCS_CFG 0x0002DD00
355 #define CONFIG_SYS_CS4_START 0x60000000
356 #define CONFIG_SYS_CS4_SIZE 0x1000
357 #define CONFIG_SYS_CS4_CFG 0x0008FC00
359 #define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
360 #define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
361 #define CONFIG_SYS_CS0_CFG 0x0002DD00
363 #if defined(CONFIG_DIGSY_REV5)
364 #define CONFIG_SYS_CS1_START CONFIG_SYS_FLASH_BASE_CS1
365 #define CONFIG_SYS_CS1_SIZE CONFIG_SYS_FLASH_SIZE
366 #define CONFIG_SYS_CS1_CFG 0x0002DD00
369 #define CONFIG_SYS_CS_BURST 0x00000000
370 #define CONFIG_SYS_CS_DEADCYCLE 0x11111111
372 #if !defined(CONFIG_SYS_LOWBOOT)
373 #define CONFIG_SYS_RESET_ADDRESS 0xfff00100
375 #define CONFIG_SYS_RESET_ADDRESS 0xff000100
381 #define CONFIG_USB_OHCI_NEW
382 #define CONFIG_SYS_OHCI_BE_CONTROLLER
384 #define CONFIG_USB_CLOCK 0x00013333
385 #define CONFIG_USB_CONFIG 0x00002000
387 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
388 #define CONFIG_SYS_USB_OHCI_REGS_BASE MPC5XXX_USB
389 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "mpc5200"
390 #define CONFIG_SYS_USB_OHCI_CPU_INIT
395 #define CONFIG_IDE_RESET
396 #define CONFIG_IDE_PREINIT
398 #define CONFIG_SYS_ATA_CS_ON_I2C2
399 #define CONFIG_SYS_IDE_MAXBUS 1
400 #define CONFIG_SYS_IDE_MAXDEVICE 1
402 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
403 #define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
404 #define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
405 #define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
406 #define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
407 #define CONFIG_SYS_ATA_STRIDE 4
409 #define CONFIG_ATAPI 1
410 #define CONFIG_LBA48 1
412 #endif /* __CONFIG_H */