1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Texas Instruments Incorporated.
5 * Lokesh Vutla <lokeshvutla@ti.com>
7 * Configuration settings for the TI DRA7XX board.
8 * See ti_omap5_common.h for omap5 common settings.
11 #ifndef __CONFIG_DRA7XX_EVM_H
12 #define __CONFIG_DRA7XX_EVM_H
14 #include <environment/ti/dfu.h>
16 #define CONFIG_IODELAY_RECALIBRATION
18 #define CONFIG_VERY_BIG_RAM
19 #define CONFIG_NR_DRAM_BANKS 2
20 #define CONFIG_MAX_MEM_MAPPED 0x80000000
22 #ifndef CONFIG_QSPI_BOOT
23 /* MMC ENV related defines */
24 #define CONFIG_SYS_MMC_ENV_DEV 1 /* SLOT2: eMMC(1) */
25 #define CONFIG_ENV_SIZE (128 << 10)
26 #define CONFIG_ENV_OFFSET 0x260000
27 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
28 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT
31 #if (CONFIG_CONS_INDEX == 1)
32 #define CONSOLEDEV "ttyO0"
33 #elif (CONFIG_CONS_INDEX == 3)
34 #define CONSOLEDEV "ttyO2"
36 #define CONFIG_SYS_NS16550_COM1 UART1_BASE /* Base EVM has UART0 */
37 #define CONFIG_SYS_NS16550_COM2 UART2_BASE /* UART2 */
38 #define CONFIG_SYS_NS16550_COM3 UART3_BASE /* UART3 */
40 #define CONFIG_ENV_EEPROM_IS_ON_I2C
41 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */
42 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
44 #define CONFIG_SYS_OMAP_ABE_SYSCK
46 #ifndef CONFIG_SPL_BUILD
48 "dfu_bufsiz=0x10000\0" \
55 #ifdef CONFIG_SPL_BUILD
56 #undef CONFIG_CMD_BOOTD
57 #ifdef CONFIG_SPL_DFU_SUPPORT
58 #define CONFIG_SPL_LOAD_FIT_ADDRESS 0x80200000
60 "dfu_bufsiz=0x10000\0" \
65 #include <configs/ti_omap5_common.h>
67 /* Enhance our eMMC support / experience. */
68 #define CONFIG_HSMMC2_8BIT
71 #define CONFIG_BOOTP_DNS2
72 #define CONFIG_BOOTP_SEND_HOSTNAME
73 #define CONFIG_NET_RETRY_COUNT 10
74 #define CONFIG_MII /* Required in net/eth.c */
78 #define CONFIG_TI_SPI_MMAP
79 #define CONFIG_SF_DEFAULT_SPEED 76800000
80 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
81 #define CONFIG_QSPI_QUAD_SUPPORT
84 * Default to using SPI for environment, etc.
85 * 0x000000 - 0x040000 : QSPI.SPL (256KiB)
86 * 0x040000 - 0x140000 : QSPI.u-boot (1MiB)
87 * 0x140000 - 0x1C0000 : QSPI.u-boot-spl-os (512KiB)
88 * 0x1C0000 - 0x1D0000 : QSPI.u-boot-env (64KiB)
89 * 0x1D0000 - 0x1E0000 : QSPI.u-boot-env.backup1 (64KiB)
90 * 0x1E0000 - 0x9E0000 : QSPI.kernel (8MiB)
91 * 0x9E0000 - 0x2000000 : USERLAND
93 #define CONFIG_SYS_SPI_KERNEL_OFFS 0x1E0000
94 #define CONFIG_SYS_SPI_ARGS_OFFS 0x140000
95 #define CONFIG_SYS_SPI_ARGS_SIZE 0x80000
96 #if defined(CONFIG_QSPI_BOOT)
97 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT
98 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
99 #define CONFIG_ENV_SIZE (64 << 10)
100 #define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64 KB sectors */
101 #define CONFIG_ENV_OFFSET 0x1C0000
102 #define CONFIG_ENV_OFFSET_REDUND 0x1D0000
106 #define CONFIG_TI_EDMA3
107 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000
109 #define CONFIG_SUPPORT_EMMC_BOOT
112 #define CONFIG_USB_XHCI_OMAP
114 #define CONFIG_OMAP_USB2PHY2_HOST
117 #define CONFIG_SCSI_AHCI_PLAT
118 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
119 #define CONFIG_SYS_SCSI_MAX_LUN 1
120 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
121 CONFIG_SYS_SCSI_MAX_LUN)
125 /* NAND: device related configs */
126 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
127 #define CONFIG_SYS_NAND_OOBSIZE 64
128 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
129 #define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
130 CONFIG_SYS_NAND_PAGE_SIZE)
131 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
132 /* NAND: driver related configs */
133 #define CONFIG_SYS_NAND_ONFI_DETECTION
134 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
135 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
136 #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
137 10, 11, 12, 13, 14, 15, 16, 17, \
138 18, 19, 20, 21, 22, 23, 24, 25, \
139 26, 27, 28, 29, 30, 31, 32, 33, \
140 34, 35, 36, 37, 38, 39, 40, 41, \
141 42, 43, 44, 45, 46, 47, 48, 49, \
142 50, 51, 52, 53, 54, 55, 56, 57, }
143 #define CONFIG_SYS_NAND_ECCSIZE 512
144 #define CONFIG_SYS_NAND_ECCBYTES 14
145 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x000c0000
146 /* NAND: SPL related configs */
147 /* NAND: SPL falcon mode configs */
148 #ifdef CONFIG_SPL_OS_BOOT
149 #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00200000 /* kernel offset */
151 #endif /* !CONFIG_NAND */
153 /* Parallel NOR Support */
154 #if defined(CONFIG_NOR)
155 /* NOR: device related configs */
156 #define CONFIG_SYS_MAX_FLASH_SECT 512
157 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
158 #define CONFIG_SYS_FLASH_SIZE (64 * 1024 * 1024) /* 64 MB */
159 /* #define CONFIG_INIT_IGNORE_ERROR */
160 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
161 #define CONFIG_SYS_FLASH_PROTECTION
162 #define CONFIG_SYS_FLASH_CFI
163 #define CONFIG_FLASH_CFI_DRIVER
164 #define CONFIG_FLASH_CFI_MTD
165 #define CONFIG_SYS_MAX_FLASH_BANKS 1
166 #define CONFIG_SYS_FLASH_BASE (0x08000000)
167 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
168 /* Reduce SPL size by removing unlikey targets */
169 #ifdef CONFIG_NOR_BOOT
170 #define CONFIG_ENV_SECT_SIZE (128 * 1024) /* 128 KiB */
171 #define CONFIG_ENV_OFFSET 0x001c0000
172 #define CONFIG_ENV_OFFSET_REDUND 0x001e0000
174 #endif /* NOR support */
176 #endif /* __CONFIG_DRA7XX_EVM_H */