3 * Graeme Russ, graeme.russ@gmail.com.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * board/config.h - configuration options, board specific
32 * Stuff still to be dealt with -
34 #define CONFIG_RTC_MC146818
37 * High Level Configuration Options
42 #define CONFIG_X86 1 /* Intel X86 CPU */
43 #define CONFIG_SYS_SC520 1 /* AMD SC520 */
44 #define CONFIG_SYS_SC520_SSI
45 #define CONFIG_SHOW_BOOT_PROGRESS 1
46 #define CONFIG_LAST_STAGE_INIT 1
49 * If CONFIG_HW_WATCHDOG is not defined, the watchdog jumper on the
50 * bottom (processor) board MUST be removed!
52 #undef CONFIG_WATCHDOG
53 #undef CONFIG_HW_WATCHDOG
55 /*-----------------------------------------------------------------------
58 #undef CONFIG_VIDEO /* No Video Hardware */
59 #undef CONFIG_CFB_CONSOLE
62 * Size of malloc() pool
64 #define CONFIG_MALLOC_SIZE (CONFIG_SYS_ENV_SIZE + 128*1024)
66 #define CONFIG_BAUDRATE 9600
68 /*-----------------------------------------------------------------------
69 * Command line configuration.
71 #include <config_cmd_default.h>
73 #define CONFIG_CMD_BDI /* bdinfo */
74 #define CONFIG_CMD_BOOTD /* bootd */
75 #define CONFIG_CMD_CONSOLE /* coninfo */
76 #define CONFIG_CMD_ECHO /* echo arguments */
77 #define CONFIG_CMD_FLASH /* flinfo, erase, protect */
78 #define CONFIG_CMD_FPGA /* FPGA configuration Support */
79 #define CONFIG_CMD_IMI /* iminfo */
80 #define CONFIG_CMD_IMLS /* List all found images */
81 #define CONFIG_CMD_IRQ /* IRQ Information */
82 #define CONFIG_CMD_ITEST /* Integer (and string) test */
83 #define CONFIG_CMD_LOADB /* loadb */
84 #define CONFIG_CMD_LOADS /* loads */
85 #define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop mtest */
86 #define CONFIG_CMD_MISC /* Misc functions like sleep etc*/
87 #undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
88 #undef CONFIG_CMD_NFS /* NFS support */
89 #define CONFIG_CMD_PCI /* PCI support */
90 #define CONFIG_CMD_RUN /* run command in env variable */
91 #define CONFIG_CMD_SAVEENV /* saveenv */
92 #define CONFIG_CMD_SETGETDCR /* DCR support on 4xx */
93 #define CONFIG_CMD_SOURCE /* "source" command Support */
94 #define CONFIG_CMD_XIMG /* Load part of Multi Image */
96 #define CONFIG_BOOTDELAY 15
97 #define CONFIG_BOOTARGS "root=/dev/mtdblock0 console=ttyS0,9600"
98 /* #define CONFIG_BOOTCOMMAND "bootm 38000000" */
100 #if defined(CONFIG_CMD_KGDB)
101 #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
102 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
106 * Miscellaneous configurable options
108 #define CONFIG_SYS_LONGHELP /* undef to save memory */
109 #define CONFIG_SYS_PROMPT "boot > " /* Monitor Command Prompt */
110 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
111 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
112 sizeof(CONFIG_SYS_PROMPT) + \
113 16) /* Print Buffer Size */
114 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
115 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
117 #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
118 #define CONFIG_SYS_MEMTEST_END 0x01000000 /* 1 ... 16 MB in DRAM */
120 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
122 #define CONFIG_SYS_HZ 1024 /* incrementer freq: 1kHz */
124 /* valid baudrates */
125 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
127 /*-----------------------------------------------------------------------
128 * SDRAM Configuration
130 #define CONFIG_SYS_SDRAM_DRCTMCTL 0x18
131 #define CONFIG_NR_DRAM_BANKS 4
133 /* CONFIG_SYS_SDRAM_DRCTMCTL Overrides the following*/
134 #undef CONFIG_SYS_SDRAM_PRECHARGE_DELAY
135 #undef CONFIG_SYS_SDRAM_REFRESH_RATE
136 #undef CONFIG_SYS_SDRAM_RAS_CAS_DELAY
137 #undef CONFIG_SYS_SDRAM_CAS_LATENCY_2T
138 #undef CONFIG_SYS_SDRAM_CAS_LATENCY_3T
140 /*-----------------------------------------------------------------------
143 #define CONFIG_SYS_SC520_HIGH_SPEED 0 /* 100 or 133MHz */
144 #undef CONFIG_SYS_SC520_RESET /* use SC520 MMCR's to reset cpu */
145 #define CONFIG_SYS_SC520_TIMER /* use SC520 swtimers */
146 #undef CONFIG_SYS_GENERIC_TIMER /* use the i8254 PIT timers */
147 #undef CONFIG_SYS_TSC_TIMER /* use the Pentium TSC timers */
148 #define CONFIG_SYS_USE_SIO_UART 0 /* prefer the uarts on the SIO to those
149 * in the SC520 on the CDP */
150 #define CONFIG_SYS_PCAT_INTERRUPTS
151 #define CONFIG_SYS_NUM_IRQS 16
153 /*-----------------------------------------------------------------------
154 * Memory organization
156 #define CONFIG_SYS_STACK_SIZE 0x8000 /* Size of bootloader stack */
157 #define CONFIG_SYS_BL_START_FLASH 0x38040000 /* Address of relocated code */
158 #define CONFIG_SYS_BL_START_RAM 0x03fd0000 /* Address of relocated code */
159 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE
160 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
161 #define CONFIG_SYS_FLASH_BASE 0x38000000 /* Boot Flash */
162 #define CONFIG_SYS_FLASH_BASE_1 0x10000000 /* StrataFlash 1 */
163 #define CONFIG_SYS_FLASH_BASE_2 0x11000000 /* StrataFlash 2 */
165 /* timeout values are in ticks */
166 #define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
167 #define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Write */
169 /* allow to overwrite serial and ethaddr */
170 #define CONFIG_ENV_OVERWRITE
172 /*-----------------------------------------------------------------------
173 * FLASH configuration
175 #define CONFIG_FLASH_CFI_DRIVER /* Use the common driver */
176 #define CONFIG_FLASH_CFI_LEGACY
177 #define CONFIG_SYS_FLASH_CFI /* Flash is CFI conformant */
178 #define CONFIG_SYS_MAX_FLASH_BANKS 3 /* max number of memory banks */
179 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, \
180 CONFIG_SYS_FLASH_BASE_1, \
181 CONFIG_SYS_FLASH_BASE_2}
182 #define CONFIG_SYS_FLASH_EMPTY_INFO
183 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
184 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
185 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
186 #define CONFIG_SYS_FLASH_LEGACY_512Kx8
188 /*-----------------------------------------------------------------------
189 * Environment configuration
191 #define CONFIG_ENV_IS_IN_FLASH 1
192 #define CONFIG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */
193 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
194 #define CONFIG_ENV_ADDR CONFIG_SYS_FLASH_BASE_1
196 #define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE_1 + \
197 CONFIG_ENV_SECT_SIZE)
198 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SECT_SIZE
201 /*-----------------------------------------------------------------------
204 #define CONFIG_PCI /* include pci support */
205 #define CONFIG_PCI_PNP /* pci plug-and-play */
206 #define CONFIG_SYS_FIRST_PCI_IRQ 10
207 #define CONFIG_SYS_SECOND_PCI_IRQ 9
208 #define CONFIG_SYS_THIRD_PCI_IRQ 11
209 #define CONFIG_SYS_FORTH_PCI_IRQ 15
211 /*-----------------------------------------------------------------------
212 * Hardware watchdog configuration
214 #define CONFIG_SYS_WATCHDOG_PIO_BIT 0x8000
215 #define CONFIG_SYS_WATCHDIG_PIO_DATA SC520_PIODATA15_0
216 #define CONFIG_SYS_WATCHDIG_PIO_CLR SC520_PIOCLR15_0
217 #define CONFIG_SYS_WATCHDIG_PIO_SET SC520_PIOSET15_0
219 /*-----------------------------------------------------------------------
222 #define CONFIG_SYS_FPGA_PROGRAM_PIO_BIT 0x2000
223 #define CONFIG_SYS_FPGA_INIT_PIO_BIT 0x4000
224 #define CONFIG_SYS_FPGA_DONE_PIO_BIT 0x8000
225 #define CONFIG_SYS_FPGA_PIO_DATA SC520_PIODATA31_16
226 #define CONFIG_SYS_FPGA_PIO_DIRECTION SC520_PIODIR31_16
227 #define CONFIG_SYS_FPGA_PIO_CLR SC520_PIOCLR31_16
228 #define CONFIG_SYS_FPGA_PIO_SET SC520_PIOSET31_16
229 #define CONFIG_SYS_FPGA_PROGRAM_BIT_DROP_TIME 1 /* milliseconds */
230 #define CONFIG_SYS_FPGA_MAX_INIT_TIME 10 /* milliseconds */
231 #define CONFIG_SYS_FPGA_MAX_FINALISE_TIME 10 /* milliseconds */
232 #define CONFIG_SYS_FPGA_SSI_DATA_RATE 8333 /* kHz (33.3333MHz xtal) */
234 #ifndef __ASSEMBLER__
235 extern unsigned long ip;
237 #define PRINTIP asm ("call next_line\n" \
242 : /* No Input Registers */ \
244 printf("IP: 0x%08lx (File: %s, Line: %d)\n", ip, __FILE__, __LINE__);
247 #endif /* __CONFIG_H */