3 * Graeme Russ, graeme.russ@gmail.com.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #include <asm/ibmpc.h>
26 * board/config.h - configuration options, board specific
33 * High Level Configuration Options
36 #define CONFIG_SYS_SC520
37 #define CONFIG_SYS_SC520_SSI
38 #define CONFIG_SHOW_BOOT_PROGRESS
39 #define CONFIG_LAST_STAGE_INIT
41 /*-----------------------------------------------------------------------
42 * Watchdog Configuration
43 * NOTE: If CONFIG_HW_WATCHDOG is NOT defined, the watchdog jumper on the
44 * bottom (processor) board MUST be removed!
46 #undef CONFIG_WATCHDOG
47 #define CONFIG_HW_WATCHDOG
49 /*-----------------------------------------------------------------------
50 * Real Time Clock Configuration
52 #define CONFIG_RTC_MC146818
53 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0
55 /*-----------------------------------------------------------------------
56 * Serial Configuration
58 #define CONFIG_CONS_INDEX 1
59 #define CONFIG_SYS_NS16550
60 #define CONFIG_SYS_NS16550_SERIAL
61 #define CONFIG_SYS_NS16550_REG_SIZE 1
62 #define CONFIG_SYS_NS16550_CLK 1843200
63 #define CONFIG_BAUDRATE 9600
64 #define CONFIG_SYS_BAUDRATE_TABLE {300, 600, 1200, 2400, 4800, \
65 9600, 19200, 38400, 115200}
66 #define CONFIG_SYS_NS16550_COM1 UART0_BASE
67 #define CONFIG_SYS_NS16550_COM2 UART1_BASE
68 #define CONFIG_SYS_NS16550_COM3 (0x1000 + UART0_BASE)
69 #define CONFIG_SYS_NS16550_COM4 (0x1000 + UART1_BASE)
70 #define CONFIG_SYS_NS16550_PORT_MAPPED
72 /*-----------------------------------------------------------------------
76 #undef CONFIG_CFB_CONSOLE
78 /*-----------------------------------------------------------------------
79 * Command line configuration.
81 #include <config_cmd_default.h>
83 #define CONFIG_CMD_BDI
84 #define CONFIG_CMD_BOOTD
85 #define CONFIG_CMD_CONSOLE
86 #define CONFIG_CMD_DATE
87 #define CONFIG_CMD_ECHO
88 #define CONFIG_CMD_FLASH
89 #define CONFIG_CMD_FPGA
90 #define CONFIG_CMD_IMI
91 #define CONFIG_CMD_IMLS
92 #define CONFIG_CMD_IRQ
93 #define CONFIG_CMD_ITEST
94 #define CONFIG_CMD_LOADB
95 #define CONFIG_CMD_LOADS
96 #define CONFIG_CMD_MEMORY
97 #define CONFIG_CMD_MISC
98 #define CONFIG_CMD_NET
100 #define CONFIG_CMD_PCI
101 #define CONFIG_CMD_PING
102 #define CONFIG_CMD_RUN
103 #define CONFIG_CMD_SAVEENV
104 #define CONFIG_CMD_SETGETDCR
105 #define CONFIG_CMD_SOURCE
106 #define CONFIG_CMD_XIMG
107 #define CONFIG_CMD_ZBOOT
109 #define CONFIG_BOOTDELAY 15
110 #define CONFIG_BOOTARGS "root=/dev/mtdblock0 console=ttyS0,9600"
112 #if defined(CONFIG_CMD_KGDB)
113 #define CONFIG_KGDB_BAUDRATE 115200
114 #define CONFIG_KGDB_SER_INDEX 2
118 * Miscellaneous configurable options
120 #define CONFIG_SYS_LONGHELP
121 #define CONFIG_SYS_PROMPT "boot > "
122 #define CONFIG_SYS_CBSIZE 256
123 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
124 sizeof(CONFIG_SYS_PROMPT) + \
126 #define CONFIG_SYS_MAXARGS 16
127 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
129 #define CONFIG_SYS_MEMTEST_START 0x00100000
130 #define CONFIG_SYS_MEMTEST_END 0x01000000
131 #define CONFIG_SYS_LOAD_ADDR 0x100000
132 #define CONFIG_SYS_HZ 1000
134 /*-----------------------------------------------------------------------
135 * SDRAM Configuration
137 #define CONFIG_SYS_SDRAM_DRCTMCTL 0x18
138 #define CONFIG_SYS_SDRAM_REFRESH_RATE 156
139 #define CONFIG_NR_DRAM_BANKS 4
141 /* CONFIG_SYS_SDRAM_DRCTMCTL Overrides the following*/
142 #undef CONFIG_SYS_SDRAM_PRECHARGE_DELAY
143 #undef CONFIG_SYS_SDRAM_RAS_CAS_DELAY
144 #undef CONFIG_SYS_SDRAM_CAS_LATENCY_2T
145 #undef CONFIG_SYS_SDRAM_CAS_LATENCY_3T
147 /*-----------------------------------------------------------------------
150 #define CONFIG_SYS_SC520_HIGH_SPEED 0
151 #define CONFIG_SYS_SC520_RESET
152 #define CONFIG_SYS_SC520_TIMER
153 #undef CONFIG_SYS_GENERIC_TIMER
154 #define CONFIG_SYS_PCAT_INTERRUPTS
155 #define CONFIG_SYS_NUM_IRQS 16
156 #define CONFIG_SYS_PC_BIOS
157 #define CONFIG_SYS_PCI_BIOS
158 #define CONFIG_SYS_X86_REALMODE
159 #define CONFIG_SYS_X86_ISR_TIMER
161 /*-----------------------------------------------------------------------
162 * Memory organization:
164 * 16kB Cache-As-RAM @ 0x19200000
166 * (128kB + Environment Sector Size) malloc pool
168 #define CONFIG_SYS_STACK_SIZE (32 * 1024)
169 #define CONFIG_SYS_CAR_ADDR 0x19200000
170 #define CONFIG_SYS_CAR_SIZE (16 * 1024)
171 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
172 #define CONFIG_SYS_MONITOR_LEN (256 * 1024)
173 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SECT_SIZE + \
175 /* allow to overwrite serial and ethaddr */
176 #define CONFIG_ENV_OVERWRITE
178 /*-----------------------------------------------------------------------
179 * FLASH configuration
180 * 512kB Boot Flash @ 0x38000000 (Monitor @ 38040000)
181 * 16MB StrataFlash #1 @ 0x10000000
182 * 16MB StrataFlash #2 @ 0x11000000
184 #define CONFIG_FLASH_CFI_DRIVER
185 #define CONFIG_FLASH_CFI_LEGACY
186 #define CONFIG_SYS_FLASH_CFI
187 #define CONFIG_SYS_MAX_FLASH_BANKS 3
188 #define CONFIG_SYS_FLASH_BASE 0x38000000
189 #define CONFIG_SYS_FLASH_BASE_1 0x10000000
190 #define CONFIG_SYS_FLASH_BASE_2 0x11000000
191 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, \
192 CONFIG_SYS_FLASH_BASE_1, \
193 CONFIG_SYS_FLASH_BASE_2}
194 #define CONFIG_SYS_FLASH_EMPTY_INFO
195 #undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
196 #define CONFIG_SYS_MAX_FLASH_SECT 128
197 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
198 #define CONFIG_SYS_FLASH_LEGACY_512Kx8
199 #define CONFIG_SYS_FLASH_ERASE_TOUT 2000 /* ms */
200 #define CONFIG_SYS_FLASH_WRITE_TOUT 2000 /* ms */
202 /*-----------------------------------------------------------------------
203 * Environment configuration
204 * - Boot flash is 512kB with 64kB sectors
205 * - StrataFlash is 32MB with 128kB sectors
206 * - Redundant embedded environment is 25% of the Boot flash
207 * - Redundant StrataFlash environment is <1% of the StrataFlash
208 * - Environment is therefore located in StrataFlash
209 * - Primary copy is located in first sector of first flash
210 * - Redundant copy is located in second sector of first flash
211 * - Stack is only 32kB, so environment size is limited to 4kB
213 #define CONFIG_ENV_IS_IN_FLASH
214 #define CONFIG_ENV_SECT_SIZE 0x20000
215 #define CONFIG_ENV_SIZE 0x01000
216 #define CONFIG_ENV_ADDR CONFIG_SYS_FLASH_BASE_1
217 #define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE_1 + \
218 CONFIG_ENV_SECT_SIZE)
219 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
221 /*-----------------------------------------------------------------------
225 #define CONFIG_PCI_PNP
226 #define CONFIG_SYS_FIRST_PCI_IRQ 10
227 #define CONFIG_SYS_SECOND_PCI_IRQ 9
228 #define CONFIG_SYS_THIRD_PCI_IRQ 11
229 #define CONFIG_SYS_FORTH_PCI_IRQ 15
231 /*-----------------------------------------------------------------------
232 * Network device (TRL8100B) support
234 #define CONFIG_RTL8139
236 /*-----------------------------------------------------------------------
237 * BOOTCS Control (for AM29LV040B-120JC)
239 * 000 0 00 0 000 11 0 011 }- 0x0033
240 * \ / | \| | \ / \| | \ /
242 * | | | | | | | +---- 3 Wait States (First Access)
243 * | | | | | | +------- Reserved
244 * | | | | | +--------- 3 Wait States (Subsequent Access)
245 * | | | | +------------- Reserved
246 * | | | +---------------- Non-Paged Mode
247 * | | +------------------ 8 Bit Wide
248 * | +--------------------- GP Bus
249 * +------------------------ Reserved
251 #define CONFIG_SYS_SC520_BOOTCS_CTRL 0x0033
253 /*-----------------------------------------------------------------------
254 * ROMCS Control (for E28F128J3A-150 StrataFlash)
256 * 000 0 01 1 000 01 0 101 }- 0x0615
257 * \ / | \| | \ / \| | \ /
259 * | | | | | | | +---- 5 Wait States (First Access)
260 * | | | | | | +------- Reserved
261 * | | | | | +--------- 1 Wait State (Subsequent Access)
262 * | | | | +------------- Reserved
263 * | | | +---------------- Paged Mode
264 * | | +------------------ 16 Bit Wide
265 * | +--------------------- GP Bus
266 * +------------------------ Reserved
268 #define CONFIG_SYS_SC520_ROMCS1_CTRL 0x0615
269 #define CONFIG_SYS_SC520_ROMCS2_CTRL 0x0615
271 /*-----------------------------------------------------------------------
272 * SC520 General Purpose Bus configuration
274 * Chip Select Offset 1 Clock Cycle
275 * Chip Select Pulse Width 8 Clock Cycles
276 * Chip Select Read Offset 2 Clock Cycles
277 * Chip Select Read Width 6 Clock Cycles
278 * Chip Select Write Offset 2 Clock Cycles
279 * Chip Select Write Width 6 Clock Cycles
280 * Chip Select Recovery Time 2 Clock Cycles
282 * Timing Diagram (from SC520 Register Set Manual - Order #22005B)
284 * |<-------------General Purpose Bus Cycle---------------->|
286 * ----------------------\__________________/------------------
287 * |<--(GPCSOFF + 1)-->|<--(GPCSPW + 1)-->|<-(GPCSRT + 1)-> |
289 * ------------------------\_______________/-------------------
290 * |<---(GPRDOFF + 1)--->|<-(GPRDW + 1)->|
292 * --------------------------\_______________/-----------------
293 * |<----(GPWROFF + 1)---->|<-(GPWRW + 1)->|
295 * ________/-----------\_______________________________________
296 * |<--->|<--------->|
302 #define CONFIG_SYS_SC520_GPCSOFF 0x00
303 #define CONFIG_SYS_SC520_GPCSPW 0x07
304 #define CONFIG_SYS_SC520_GPRDOFF 0x01
305 #define CONFIG_SYS_SC520_GPRDW 0x05
306 #define CONFIG_SYS_SC520_GPWROFF 0x01
307 #define CONFIG_SYS_SC520_GPWRW 0x05
308 #define CONFIG_SYS_SC520_GPCSRT 0x01
310 /*-----------------------------------------------------------------------
311 * SC520 Programmable I/O configuration
313 * Pin Mode Dir. Description
314 * ----------------------------------------------------------------------
315 * PIO0 PIO Output Unused
316 * PIO1 GPBHE# Output GP Bus Byte High Enable (active low)
317 * PIO2 PIO Output Auxiliary power output enable
318 * PIO3 GPAEN Output GP Bus Address Enable
319 * PIO4 PIO Output Top Board Enable (active low)
320 * PIO5 PIO Output StrataFlash 16 bit mode (low = 8 bit mode)
321 * PIO6 PIO Input Data output of Power Supply ADC
322 * PIO7 PIO Output Clock input to Power Supply ADC
323 * PIO8 PIO Output Chip Select input of Power Supply ADC
324 * PIO9 PIO Output StrataFlash 1 Reset / Power Down (active low)
325 * PIO10 PIO Output StrataFlash 2 Reset / Power Down (active low)
326 * PIO11 PIO Input StrataFlash 1 Status
327 * PIO12 PIO Input StrataFlash 2 Status
328 * PIO13 GPIRQ10# Input Can Bus / I2C IRQ (active low)
329 * PIO14 PIO Input Low Input Voltage Warning (active low)
330 * PIO15 PIO Output Watchdog (must toggle at least every 1.6s)
331 * PIO16 PIO Input Power Fail
332 * PIO17 GPIRQ6 Input Compact Flash 1 IRQ (active low)
333 * PIO18 GPIRQ5 Input Compact Flash 2 IRQ (active low)
334 * PIO19 GPIRQ4# Input Dual-Port RAM IRQ (active low)
335 * PIO20 GPIRQ3 Input UART D IRQ
336 * PIO21 GPIRQ2 Input UART C IRQ
337 * PIO22 GPIRQ1 Input UART B IRQ
338 * PIO23 GPIRQ0 Input UART A IRQ
339 * PIO24 GPDBUFOE# Output GP Bus Data Bus Buffer Output Enable
340 * PIO25 PIO Input Battery OK Indication
341 * PIO26 GPMEMCS16# Input GP Bus Memory Chip-Select 16-bit access
342 * PIO27 GPCS0# Output SRAM 1 Chip Select
343 * PIO28 PIO Input Top Board UART CTS
344 * PIO29 PIO Output FPGA Program Mode (active low)
345 * PIO30 PIO Input FPGA Initialised (active low)
346 * PIO31 PIO Input FPGA Done (active low)
348 #define CONFIG_SYS_SC520_PIOPFS15_0 0x200a
349 #define CONFIG_SYS_SC520_PIOPFS31_16 0x0dfe
350 #define CONFIG_SYS_SC520_PIODIR15_0 0x87bf
351 #define CONFIG_SYS_SC520_PIODIR31_16 0x2900
353 /*-----------------------------------------------------------------------
356 #define CONFIG_SYS_ENET_AUX_PWR 0x0004
357 #define CONFIG_SYS_ENET_TOP_BRD_PWR 0x0010
358 #define CONFIG_SYS_ENET_SF_WIDTH 0x0020
359 #define CONFIG_SYS_ENET_PWR_ADC_DATA 0x0040
360 #define CONFIG_SYS_ENET_PWR_ADC_CLK 0x0080
361 #define CONFIG_SYS_ENET_PWR_ADC_CS 0x0100
362 #define CONFIG_SYS_ENET_SF1_MODE 0x0200
363 #define CONFIG_SYS_ENET_SF2_MODE 0x0400
364 #define CONFIG_SYS_ENET_SF1_STATUS 0x0800
365 #define CONFIG_SYS_ENET_SF2_STATUS 0x1000
366 #define CONFIG_SYS_ENET_PWR_STATUS 0x4000
367 #define CONFIG_SYS_ENET_WATCHDOG 0x8000
369 #define CONFIG_SYS_ENET_PWR_FAIL 0x0001
370 #define CONFIG_SYS_ENET_BAT_OK 0x0200
371 #define CONFIG_SYS_ENET_TOP_BRD_CTS 0x1000
372 #define CONFIG_SYS_ENET_FPGA_PROG 0x2000
373 #define CONFIG_SYS_ENET_FPGA_INIT 0x4000
374 #define CONFIG_SYS_ENET_FPGA_DONE 0x8000
376 /*-----------------------------------------------------------------------
377 * Chip Select Pin Function Select
379 * 1 1 1 1 1 0 0 0 }- 0xf8
381 * | | | | | | | +--- Reserved
382 * | | | | | | +----- GPCS1_SEL = ROMCS1#
383 * | | | | | +------- GPCS2_SEL = ROMCS2#
384 * | | | | +--------- GPCS3_SEL = GPCS3
385 * | | | +----------- GPCS4_SEL = GPCS4
386 * | | +------------- GPCS5_SEL = GPCS5
387 * | +--------------- GPCS6_SEL = GPCS6
388 * +----------------- GPCS7_SEL = GPCS7
390 #define CONFIG_SYS_SC520_CSPFS 0xf8
392 /*-----------------------------------------------------------------------
393 * Clock Select (CLKTIMER[CLKTEST] pin)
395 * 0 111 00 1 0 }- 0x72
397 * | | | | +--- Pin Disabled
398 * | | | +----- Pin is an output
399 * | | +------- Reserved
400 * | +----------- Disabled (pin stays Low)
401 * +-------------- Reserved
403 #define CONFIG_SYS_SC520_CLKSEL 0x72
405 /*-----------------------------------------------------------------------
406 * Address Decode Control
408 * 0 00 0 0 0 0 0 }- 0x00
410 * | | | | | | +--- Integrated UART 1 is enabled
411 * | | | | | +----- Integrated UART 2 is enabled
412 * | | | | +------- Integrated RTC is enabled
413 * | | | +--------- Reserved
414 * | | +----------- I/O Hole accesses are forwarded to the external GP bus
415 * | +------------- Reserved
416 * +---------------- Write-protect violations do not generate an IRQ
418 #define CONFIG_SYS_SC520_ADDDECCTL 0x00
420 /*-----------------------------------------------------------------------
423 * 00000 1 1 1 }- 0x07
425 * | | | +--- Transmit TC interrupt enable
426 * | | +----- Receive TC interrupt enable
427 * | +------- 1.8432 MHz
428 * +----------- Reserved
430 #define CONFIG_SYS_SC520_UART1CTL 0x07
431 #define CONFIG_SYS_SC520_UART2CTL 0x07
433 /*-----------------------------------------------------------------------
434 * System Arbiter Control
436 * 00000 1 1 0 }- 0x06
438 * | | | +--- Disable PCI Bus Arbiter Grant Time-Out Interrupt
439 * | | +----- The system arbiter operates in concurrent mode
440 * | +------- Park the PCI bus on the last master that acquired the bus
441 * +----------- Reserved
443 #define CONFIG_SYS_SC520_SYSARBCTL 0x06
445 /*-----------------------------------------------------------------------
446 * System Arbiter Master Enable
448 * 00000000000 0 0 0 1 1 }- 0x06
449 * \_________/ | | | | |
450 * | | | | | +--- PCI master REQ0 enabled (Ethernet 1)
451 * | | | | +----- PCI master REQ1 enabled (Ethernet 2)
452 * | | | +------- PCI master REQ2 disabled
453 * | | +--------- PCI master REQ3 disabled
454 * | +----------- PCI master REQ4 disabled
455 * +------------------ Reserved
457 #define CONFIG_SYS_SC520_SYSARBMENB 0x0003
459 /*-----------------------------------------------------------------------
460 * System Arbiter Master Enable
462 * 0 0000 0 00 0000 1 000 }- 0x06
463 * | \__/ | \| \__/ | \_/
464 * | | | | | | +---- Reserved
465 * | | | | | +------- Enable CPU-to-PCI bus write posting
466 * | | | | +---------- Reserved
467 * | | | +-------------- PCI bus reads to SDRAM are not automatically
469 * | | +----------------- Target read FIFOs are not snooped during write
471 * | +-------------------- Reserved
472 * +------------------------ Deassert the PCI bus reset signal
474 #define CONFIG_SYS_SC520_HBCTL 0x08
476 /*-----------------------------------------------------------------------
477 * PAR for Boot Flash - 512kB @ 0x38000000, BOOTCS
478 * 100 0 1 0 1 00000000111 11100000000000 }- 0x8a01f800
479 * \ / | | | | \----+----/ \-----+------/
480 * | | | | | | +---------- Start at 0x38000000
481 * | | | | | +----------------------- 512kB Region Size
482 * | | | | | ((7 + 1) * 64kB)
483 * | | | | +------------------------------ 64kB Page Size
484 * | | | +-------------------------------- Writes Enabled (So it can be
485 * | | | reprogrammed!)
486 * | | +---------------------------------- Caching Disabled
487 * | +------------------------------------ Execution Enabled
488 * +--------------------------------------- BOOTCS
490 #define CONFIG_SYS_SC520_BOOTCS_PAR 0x8a01f800
492 /*-----------------------------------------------------------------------
493 * Cache-As-RAM (Targets Boot Flash)
495 * 100 1 0 0 0 0001111 011001001000000000 }- 0x903d9200
496 * \ / | | | | \--+--/ \-------+--------/
497 * | | | | | | +------------ Start at 0x19200000
498 * | | | | | +------------------------- 64k Region Size
499 * | | | | | ((15 + 1) * 4kB)
500 * | | | | +------------------------------ 4kB Page Size
501 * | | | +-------------------------------- Writes Enabled
502 * | | +---------------------------------- Caching Enabled
503 * | +------------------------------------ Execution Prevented
504 * +--------------------------------------- BOOTCS
506 #define CONFIG_SYS_SC520_CAR_PAR 0x903d9200
508 /*-----------------------------------------------------------------------
509 * PAR for Low Level I/O (LEDs, Hex Switches etc) - 33 Bytes @ 0x1000, GPCS6
511 * 001 110 0 000100000 0001000000000000 }- 0x38201000
512 * \ / \ / | \---+---/ \------+-------/
513 * | | | | +----------- Start at 0x00001000
514 * | | | +------------------------ 33 Bytes (0x20 + 1)
515 * | | +------------------------------ Ignored
516 * | +--------------------------------- GPCS6
517 * +------------------------------------- GP Bus I/O
519 #define CONFIG_SYS_SC520_LLIO_PAR 0x38201000
521 /*-----------------------------------------------------------------------
522 * PAR for Compact Flash Port #1 - 4kB @ 0x200000000, CS5
523 * PAR for Compact Flash Port #2 - 4kB @ 0x200010000, CS7
525 * 010 101 0 0000000 100000000000000000 }- 0x54020000
526 * 010 111 0 0000000 100000000000000001 }- 0x5c020001
527 * \ / \ / | \--+--/ \-------+--------/
528 * | | | | +------------ Start at 0x200000000
529 * | | | | 0x200010000
530 * | | | +------------------------- 4kB Region Size
531 * | | | ((0 + 1) * 4kB)
532 * | | +------------------------------ 4k Page Size
533 * | +--------------------------------- GPCS5
535 * +------------------------------------- GP Bus Memory
537 #define CONFIG_SYS_SC520_CF1_PAR 0x54020000
538 #define CONFIG_SYS_SC520_CF2_PAR 0x5c020001
540 /*-----------------------------------------------------------------------
541 * PAR for Extra 16550 UART A - 8 bytes @ 0x013f8, GPCS0
542 * PAR for Extra 16550 UART B - 8 bytes @ 0x012f8, GPCS3
543 * PAR for Extra 16550 UART C - 8 bytes @ 0x011f8, GPCS4
544 * PAR for Extra 16550 UART D - 8 bytes @ 0x010f8, GPCS5
546 * 001 000 0 000000111 0001001111111000 }- 0x200713f8
547 * 001 011 0 000000111 0001001011111000 }- 0x2c0712f8
548 * 001 011 0 000000111 0001001011111000 }- 0x300711f8
549 * 001 011 0 000000111 0001001011111000 }- 0x340710f8
550 * \ / \ / | \---+---/ \------+-------/
551 * | | | | +----------- Start at 0x013f8
555 * | | | +------------------------ 33 Bytes (32 + 1)
556 * | | +------------------------------ Ignored
557 * | +--------------------------------- GPCS6
558 * +------------------------------------- GP Bus I/O
560 #define CONFIG_SYS_SC520_UARTA_PAR 0x200713f8
561 #define CONFIG_SYS_SC520_UARTB_PAR 0x2c0712f8
562 #define CONFIG_SYS_SC520_UARTC_PAR 0x300711f8
563 #define CONFIG_SYS_SC520_UARTD_PAR 0x340710f8
565 /*-----------------------------------------------------------------------
566 * PAR for StrataFlash #1 - 16MB @ 0x10000000, ROMCS1
567 * PAR for StrataFlash #2 - 16MB @ 0x11000000, ROMCS2
569 * 101 0 1 0 1 00011111111 01000000000000 }- 0xaa3fd000
570 * 110 0 1 0 1 00011111111 01000100000000 }- 0xca3fd100
571 * \ / | | | | \----+----/ \-----+------/
572 * | | | | | | +---------- Start at 0x10000000
573 * | | | | | | 0x11000000
574 * | | | | | +----------------------- 16MB Region Size
575 * | | | | | ((255 + 1) * 64kB)
576 * | | | | +------------------------------ 64kB Page Size
577 * | | | +-------------------------------- Writes Enabled
578 * | | +---------------------------------- Caching Disabled
579 * | +------------------------------------ Execution Enabled
580 * +--------------------------------------- ROMCS1
583 #define CONFIG_SYS_SC520_SF1_PAR 0xaa3fd000
584 #define CONFIG_SYS_SC520_SF2_PAR 0xca3fd100
586 /*-----------------------------------------------------------------------
587 * PAR for SRAM #1 - 1MB @ 0x19000000, GPCS0
588 * PAR for SRAM #2 - 1MB @ 0x19100000, GPCS3
590 * 010 000 1 00000001111 01100100000000 }- 0x4203d900
591 * 010 011 1 00000001111 01100100010000 }- 0x4e03d910
592 * \ / \ / | \----+----/ \-----+------/
593 * | | | | +---------- Start at 0x19000000
595 * | | | +----------------------- 1MB Region Size
596 * | | | ((15 + 1) * 64kB)
597 * | | +------------------------------ 64kB Page Size
598 * | +--------------------------------- GPCS0
600 * +------------------------------------- GP Bus Memory
602 #define CONFIG_SYS_SC520_SRAM1_PAR 0x4203d900
603 #define CONFIG_SYS_SC520_SRAM2_PAR 0x4e03d910
605 /*-----------------------------------------------------------------------
606 * PAR for Dual-Port RAM - 4kB @ 0x18100000, GPCS4
608 * 010 100 0 00000000 11000000100000000 }- 0x50018100
609 * \ / \ / | \---+--/ \-------+-------/
610 * | | | | +----------- Start at 0x18100000
611 * | | | +------------------------ 4kB Region Size
612 * | | | ((0 + 1) * 4kB)
613 * | | +------------------------------ 4kB Page Size
614 * | +--------------------------------- GPCS4
615 * +------------------------------------- GP Bus Memory
617 #define CONFIG_SYS_SC520_DPRAM_PAR 0x50018100
619 #endif /* __CONFIG_H */