3 * Graeme Russ, graeme.russ@gmail.com.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #include <asm/ibmpc.h>
26 * board/config.h - configuration options, board specific
33 * High Level Configuration Options
37 #define CONFIG_SYS_SC520
38 #define CONFIG_SYS_SC520_SSI
39 #define CONFIG_SHOW_BOOT_PROGRESS
40 #define CONFIG_LAST_STAGE_INIT
42 /*-----------------------------------------------------------------------
43 * Watchdog Configuration
44 * NOTE: If CONFIG_HW_WATCHDOG is NOT defined, the watchdog jumper on the
45 * bottom (processor) board MUST be removed!
47 #undef CONFIG_WATCHDOG
48 #define CONFIG_HW_WATCHDOG
50 /*-----------------------------------------------------------------------
51 * Real Time Clock Configuration
53 #define CONFIG_RTC_MC146818
54 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0
56 /*-----------------------------------------------------------------------
57 * Serial Configuration
59 #define CONFIG_SERIAL_MULTI
60 #define CONFIG_CONS_INDEX 1
61 #define CONFIG_SYS_NS16550
62 #define CONFIG_SYS_NS16550_SERIAL
63 #define CONFIG_SYS_NS16550_REG_SIZE 1
64 #define CONFIG_SYS_NS16550_CLK 1843200
65 #define CONFIG_BAUDRATE 9600
66 #define CONFIG_SYS_BAUDRATE_TABLE {300, 600, 1200, 2400, 4800, \
67 9600, 19200, 38400, 115200}
68 #define CONFIG_SYS_NS16550_COM1 UART0_BASE
69 #define CONFIG_SYS_NS16550_COM2 UART1_BASE
70 #define CONFIG_SYS_NS16550_COM3 (0x1000 + UART0_BASE)
71 #define CONFIG_SYS_NS16550_COM4 (0x1000 + UART1_BASE)
72 #define CONFIG_SYS_NS16550_PORT_MAPPED
74 /*-----------------------------------------------------------------------
78 #undef CONFIG_CFB_CONSOLE
80 /*-----------------------------------------------------------------------
81 * Command line configuration.
83 #include <config_cmd_default.h>
85 #define CONFIG_CMD_BDI
86 #define CONFIG_CMD_BOOTD
87 #define CONFIG_CMD_CONSOLE
88 #define CONFIG_CMD_DATE
89 #define CONFIG_CMD_ECHO
90 #define CONFIG_CMD_FLASH
91 #define CONFIG_CMD_FPGA
92 #define CONFIG_CMD_IMI
93 #define CONFIG_CMD_IMLS
94 #define CONFIG_CMD_IRQ
95 #define CONFIG_CMD_ITEST
96 #define CONFIG_CMD_LOADB
97 #define CONFIG_CMD_LOADS
98 #define CONFIG_CMD_MEMORY
99 #define CONFIG_CMD_MISC
100 #define CONFIG_CMD_NET
101 #undef CONFIG_CMD_NFS
102 #define CONFIG_CMD_PCI
103 #define CONFIG_CMD_PING
104 #define CONFIG_CMD_RUN
105 #define CONFIG_CMD_SAVEENV
106 #define CONFIG_CMD_SETGETDCR
107 #define CONFIG_CMD_SOURCE
108 #define CONFIG_CMD_XIMG
110 #define CONFIG_BOOTDELAY 15
111 #define CONFIG_BOOTARGS "root=/dev/mtdblock0 console=ttyS0,9600"
113 #if defined(CONFIG_CMD_KGDB)
114 #define CONFIG_KGDB_BAUDRATE 115200
115 #define CONFIG_KGDB_SER_INDEX 2
119 * Miscellaneous configurable options
121 #define CONFIG_SYS_LONGHELP
122 #define CONFIG_SYS_PROMPT "boot > "
123 #define CONFIG_SYS_CBSIZE 256
124 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
125 sizeof(CONFIG_SYS_PROMPT) + \
127 #define CONFIG_SYS_MAXARGS 16
128 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
130 #define CONFIG_SYS_MEMTEST_START 0x00100000
131 #define CONFIG_SYS_MEMTEST_END 0x01000000
132 #define CONFIG_SYS_LOAD_ADDR 0x100000
133 #define CONFIG_SYS_HZ 1000
135 /*-----------------------------------------------------------------------
136 * SDRAM Configuration
138 #define CONFIG_SYS_SDRAM_DRCTMCTL 0x18
139 #define CONFIG_SYS_SDRAM_REFRESH_RATE 156
140 #define CONFIG_NR_DRAM_BANKS 4
142 /* CONFIG_SYS_SDRAM_DRCTMCTL Overrides the following*/
143 #undef CONFIG_SYS_SDRAM_PRECHARGE_DELAY
144 #undef CONFIG_SYS_SDRAM_RAS_CAS_DELAY
145 #undef CONFIG_SYS_SDRAM_CAS_LATENCY_2T
146 #undef CONFIG_SYS_SDRAM_CAS_LATENCY_3T
148 /*-----------------------------------------------------------------------
151 #define CONFIG_SYS_SC520_HIGH_SPEED 0
152 #define CONFIG_SYS_SC520_RESET
153 #define CONFIG_SYS_SC520_TIMER
154 #undef CONFIG_SYS_GENERIC_TIMER
155 #define CONFIG_SYS_PCAT_INTERRUPTS
156 #define CONFIG_SYS_NUM_IRQS 16
158 /*-----------------------------------------------------------------------
159 * Memory organization:
163 #define CONFIG_SYS_STACK_SIZE 0x8000
164 #define CONFIG_SYS_CAR_ADDR 0x19200000
165 #define CONFIG_SYS_CAR_SIZE 0x00004000
166 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_CAR_ADDR + \
168 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
169 #define CONFIG_SYS_MONITOR_LEN (256 * 1024)
170 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
171 /* Address of temporary Global Data */
172 #define CONFIG_SYS_INIT_GD_ADDR 0x19040000
175 /* allow to overwrite serial and ethaddr */
176 #define CONFIG_ENV_OVERWRITE
178 /*-----------------------------------------------------------------------
179 * FLASH configuration
180 * 512kB Boot Flash @ 0x38000000 (Monitor @ 38040000)
181 * 16MB StrataFlash #1 @ 0x10000000
182 * 16MB StrataFlash #2 @ 0x11000000
184 #define CONFIG_FLASH_CFI_DRIVER
185 #define CONFIG_FLASH_CFI_LEGACY
186 #define CONFIG_SYS_FLASH_CFI
187 #define CONFIG_SYS_MAX_FLASH_BANKS 3
188 #define CONFIG_SYS_FLASH_BASE 0x38000000
189 #define CONFIG_SYS_FLASH_BASE_1 0x10000000
190 #define CONFIG_SYS_FLASH_BASE_2 0x11000000
191 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, \
192 CONFIG_SYS_FLASH_BASE_1, \
193 CONFIG_SYS_FLASH_BASE_2}
194 #define CONFIG_SYS_FLASH_EMPTY_INFO
195 #undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
196 #define CONFIG_SYS_MAX_FLASH_SECT 128
197 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
198 #define CONFIG_SYS_FLASH_LEGACY_512Kx8
199 #define CONFIG_SYS_FLASH_ERASE_TOUT 2000 /* ms */
200 #define CONFIG_SYS_FLASH_WRITE_TOUT 2000 /* ms */
201 /*-----------------------------------------------------------------------
202 * Environment configuration
204 #define CONFIG_ENV_IS_IN_FLASH
205 #define CONFIG_ENV_SECT_SIZE 0x20000
206 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
207 #define CONFIG_ENV_ADDR CONFIG_SYS_FLASH_BASE_1
209 #define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE_1 + \
210 CONFIG_ENV_SECT_SIZE)
211 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SECT_SIZE
213 /*-----------------------------------------------------------------------
217 #define CONFIG_PCI_PNP
218 #define CONFIG_SYS_FIRST_PCI_IRQ 10
219 #define CONFIG_SYS_SECOND_PCI_IRQ 9
220 #define CONFIG_SYS_THIRD_PCI_IRQ 11
221 #define CONFIG_SYS_FORTH_PCI_IRQ 15
223 /*-----------------------------------------------------------------------
224 * Network device (TRL8100B) support
226 #define CONFIG_NET_MULTI
227 #define CONFIG_RTL8139
229 /*-----------------------------------------------------------------------
230 * BOOTCS Control (for AM29LV040B-120JC)
232 * 000 0 00 0 000 11 0 011 }- 0x0033
233 * \ / | \| | \ / \| | \ /
235 * | | | | | | | +---- 3 Wait States (First Access)
236 * | | | | | | +------- Reserved
237 * | | | | | +--------- 3 Wait States (Subsequent Access)
238 * | | | | +------------- Reserved
239 * | | | +---------------- Non-Paged Mode
240 * | | +------------------ 8 Bit Wide
241 * | +--------------------- GP Bus
242 * +------------------------ Reserved
244 #define CONFIG_SYS_SC520_BOOTCS_CTRL 0x0033
246 /*-----------------------------------------------------------------------
247 * ROMCS Control (for E28F128J3A-150 StrataFlash)
249 * 000 0 01 1 000 01 0 101 }- 0x0615
250 * \ / | \| | \ / \| | \ /
252 * | | | | | | | +---- 5 Wait States (First Access)
253 * | | | | | | +------- Reserved
254 * | | | | | +--------- 1 Wait State (Subsequent Access)
255 * | | | | +------------- Reserved
256 * | | | +---------------- Paged Mode
257 * | | +------------------ 16 Bit Wide
258 * | +--------------------- GP Bus
259 * +------------------------ Reserved
261 #define CONFIG_SYS_SC520_ROMCS1_CTRL 0x0615
262 #define CONFIG_SYS_SC520_ROMCS2_CTRL 0x0615
264 /*-----------------------------------------------------------------------
265 * SC520 General Purpose Bus configuration
267 * Chip Select Offset 1 Clock Cycle
268 * Chip Select Pulse Width 8 Clock Cycles
269 * Chip Select Read Offset 2 Clock Cycles
270 * Chip Select Read Width 6 Clock Cycles
271 * Chip Select Write Offset 2 Clock Cycles
272 * Chip Select Write Width 6 Clock Cycles
273 * Chip Select Recovery Time 2 Clock Cycles
275 * Timing Diagram (from SC520 Register Set Manual - Order #22005B)
277 * |<-------------General Purpose Bus Cycle---------------->|
279 * ----------------------\__________________/------------------
280 * |<--(GPCSOFF + 1)-->|<--(GPCSPW + 1)-->|<-(GPCSRT + 1)-> |
282 * ------------------------\_______________/-------------------
283 * |<---(GPRDOFF + 1)--->|<-(GPRDW + 1)->|
285 * --------------------------\_______________/-----------------
286 * |<----(GPWROFF + 1)---->|<-(GPWRW + 1)->|
288 * ________/-----------\_______________________________________
289 * |<--->|<--------->|
295 #define CONFIG_SYS_SC520_GPCSOFF 0x00
296 #define CONFIG_SYS_SC520_GPCSPW 0x07
297 #define CONFIG_SYS_SC520_GPRDOFF 0x01
298 #define CONFIG_SYS_SC520_GPRDW 0x05
299 #define CONFIG_SYS_SC520_GPWROFF 0x01
300 #define CONFIG_SYS_SC520_GPWRW 0x05
301 #define CONFIG_SYS_SC520_GPCSRT 0x01
303 /*-----------------------------------------------------------------------
304 * SC520 Programmable I/O configuration
306 * Pin Mode Dir. Description
307 * ----------------------------------------------------------------------
308 * PIO0 PIO Output Unused
309 * PIO1 GPBHE# Output GP Bus Byte High Enable (active low)
310 * PIO2 PIO Output Auxiliary power output enable
311 * PIO3 GPAEN Output GP Bus Address Enable
312 * PIO4 PIO Output Top Board Enable (active low)
313 * PIO5 PIO Output StrataFlash 16 bit mode (low = 8 bit mode)
314 * PIO6 PIO Input Data output of Power Supply ADC
315 * PIO7 PIO Output Clock input to Power Supply ADC
316 * PIO8 PIO Output Chip Select input of Power Supply ADC
317 * PIO9 PIO Output StrataFlash 1 Reset / Power Down (active low)
318 * PIO10 PIO Output StrataFlash 2 Reset / Power Down (active low)
319 * PIO11 PIO Input StrataFlash 1 Status
320 * PIO12 PIO Input StrataFlash 2 Status
321 * PIO13 GPIRQ10# Input Can Bus / I2C IRQ (active low)
322 * PIO14 PIO Input Low Input Voltage Warning (active low)
323 * PIO15 PIO Output Watchdog (must toggle at least every 1.6s)
324 * PIO16 PIO Input Power Fail
325 * PIO17 GPIRQ6 Input Compact Flash 1 IRQ (active low)
326 * PIO18 GPIRQ5 Input Compact Flash 2 IRQ (active low)
327 * PIO19 GPIRQ4# Input Dual-Port RAM IRQ (active low)
328 * PIO20 GPIRQ3 Input UART D IRQ
329 * PIO21 GPIRQ2 Input UART C IRQ
330 * PIO22 GPIRQ1 Input UART B IRQ
331 * PIO23 GPIRQ0 Input UART A IRQ
332 * PIO24 GPDBUFOE# Output GP Bus Data Bus Buffer Output Enable
333 * PIO25 PIO Input Battery OK Indication
334 * PIO26 GPMEMCS16# Input GP Bus Memory Chip-Select 16-bit access
335 * PIO27 GPCS0# Output SRAM 1 Chip Select
336 * PIO28 PIO Input Top Board UART CTS
337 * PIO29 PIO Output FPGA Program Mode (active low)
338 * PIO30 PIO Input FPGA Initialised (active low)
339 * PIO31 PIO Input FPGA Done (active low)
341 #define CONFIG_SYS_SC520_PIOPFS15_0 0x200a
342 #define CONFIG_SYS_SC520_PIOPFS31_16 0x0dfe
343 #define CONFIG_SYS_SC520_PIODIR15_0 0x87bf
344 #define CONFIG_SYS_SC520_PIODIR31_16 0x2900
346 /*-----------------------------------------------------------------------
349 #define CONFIG_SYS_ENET_AUX_PWR 0x0004
350 #define CONFIG_SYS_ENET_TOP_BRD_PWR 0x0010
351 #define CONFIG_SYS_ENET_SF_WIDTH 0x0020
352 #define CONFIG_SYS_ENET_PWR_ADC_DATA 0x0040
353 #define CONFIG_SYS_ENET_PWR_ADC_CLK 0x0080
354 #define CONFIG_SYS_ENET_PWR_ADC_CS 0x0100
355 #define CONFIG_SYS_ENET_SF1_MODE 0x0200
356 #define CONFIG_SYS_ENET_SF2_MODE 0x0400
357 #define CONFIG_SYS_ENET_SF1_STATUS 0x0800
358 #define CONFIG_SYS_ENET_SF2_STATUS 0x1000
359 #define CONFIG_SYS_ENET_PWR_STATUS 0x4000
360 #define CONFIG_SYS_ENET_WATCHDOG 0x8000
362 #define CONFIG_SYS_ENET_PWR_FAIL 0x0001
363 #define CONFIG_SYS_ENET_BAT_OK 0x0200
364 #define CONFIG_SYS_ENET_TOP_BRD_CTS 0x1000
365 #define CONFIG_SYS_ENET_FPGA_PROG 0x2000
366 #define CONFIG_SYS_ENET_FPGA_INIT 0x4000
367 #define CONFIG_SYS_ENET_FPGA_DONE 0x8000
369 /*-----------------------------------------------------------------------
370 * Chip Select Pin Function Select
372 * 1 1 1 1 1 0 0 0 }- 0xf8
374 * | | | | | | | +--- Reserved
375 * | | | | | | +----- GPCS1_SEL = ROMCS1#
376 * | | | | | +------- GPCS2_SEL = ROMCS2#
377 * | | | | +--------- GPCS3_SEL = GPCS3
378 * | | | +----------- GPCS4_SEL = GPCS4
379 * | | +------------- GPCS5_SEL = GPCS5
380 * | +--------------- GPCS6_SEL = GPCS6
381 * +----------------- GPCS7_SEL = GPCS7
383 #define CONFIG_SYS_SC520_CSPFS 0xf8
385 /*-----------------------------------------------------------------------
386 * Clock Select (CLKTIMER[CLKTEST] pin)
388 * 0 111 00 1 0 }- 0x72
390 * | | | | +--- Pin Disabled
391 * | | | +----- Pin is an output
392 * | | +------- Reserved
393 * | +----------- Disabled (pin stays Low)
394 * +-------------- Reserved
396 #define CONFIG_SYS_SC520_CLKSEL 0x72
398 /*-----------------------------------------------------------------------
399 * Address Decode Control
401 * 0 00 0 0 0 0 0 }- 0x00
403 * | | | | | | +--- Integrated UART 1 is enabled
404 * | | | | | +----- Integrated UART 2 is enabled
405 * | | | | +------- Integrated RTC is enabled
406 * | | | +--------- Reserved
407 * | | +----------- I/O Hole accesses are forwarded to the external GP bus
408 * | +------------- Reserved
409 * +---------------- Write-protect violations do not generate an IRQ
411 #define CONFIG_SYS_SC520_ADDDECCTL 0x00
413 /*-----------------------------------------------------------------------
416 * 00000 1 1 1 }- 0x07
418 * | | | +--- Transmit TC interrupt enable
419 * | | +----- Receive TC interrupt enable
420 * | +------- 1.8432 MHz
421 * +----------- Reserved
423 #define CONFIG_SYS_SC520_UART1CTL 0x07
424 #define CONFIG_SYS_SC520_UART2CTL 0x07
426 /*-----------------------------------------------------------------------
427 * System Arbiter Control
429 * 00000 1 1 0 }- 0x06
431 * | | | +--- Disable PCI Bus Arbiter Grant Time-Out Interrupt
432 * | | +----- The system arbiter operates in concurrent mode
433 * | +------- Park the PCI bus on the last master that acquired the bus
434 * +----------- Reserved
436 #define CONFIG_SYS_SC520_SYSARBCTL 0x06
438 /*-----------------------------------------------------------------------
439 * System Arbiter Master Enable
441 * 00000000000 0 0 0 1 1 }- 0x06
442 * \_________/ | | | | |
443 * | | | | | +--- PCI master REQ0 enabled (Ethernet 1)
444 * | | | | +----- PCI master REQ1 enabled (Ethernet 2)
445 * | | | +------- PCI master REQ2 disabled
446 * | | +--------- PCI master REQ3 disabled
447 * | +----------- PCI master REQ4 disabled
448 * +------------------ Reserved
450 #define CONFIG_SYS_SC520_SYSARBMENB 0x0003
452 /*-----------------------------------------------------------------------
453 * System Arbiter Master Enable
455 * 0 0000 0 00 0000 1 000 }- 0x06
456 * | \__/ | \| \__/ | \_/
457 * | | | | | | +---- Reserved
458 * | | | | | +------- Enable CPU-to-PCI bus write posting
459 * | | | | +---------- Reserved
460 * | | | +-------------- PCI bus reads to SDRAM are not automatically
462 * | | +----------------- Target read FIFOs are not snooped during write
464 * | +-------------------- Reserved
465 * +------------------------ Deassert the PCI bus reset signal
467 #define CONFIG_SYS_SC520_HBCTL 0x08
469 /*-----------------------------------------------------------------------
470 * PAR for Boot Flash - 512kB @ 0x38000000, BOOTCS
471 * 100 0 1 0 1 00000000111 11100000000000 }- 0x8a01f800
472 * \ / | | | | \----+----/ \-----+------/
473 * | | | | | | +---------- Start at 0x38000000
474 * | | | | | +----------------------- 512kB Region Size
475 * | | | | | ((7 + 1) * 64kB)
476 * | | | | +------------------------------ 64kB Page Size
477 * | | | +-------------------------------- Writes Enabled (So it can be
478 * | | | reprogrammed!)
479 * | | +---------------------------------- Caching Disabled
480 * | +------------------------------------ Execution Enabled
481 * +--------------------------------------- BOOTCS
483 #define CONFIG_SYS_SC520_BOOTCS_PAR 0x8a01f800
485 /*-----------------------------------------------------------------------
486 * Cache-As-RAM (Targets Boot Flash)
488 * 100 1 0 0 0 0001111 011001001000000000 }- 0x903d9200
489 * \ / | | | | \--+--/ \-------+--------/
490 * | | | | | | +------------ Start at 0x19200000
491 * | | | | | +------------------------- 64k Region Size
492 * | | | | | ((15 + 1) * 4kB)
493 * | | | | +------------------------------ 4kB Page Size
494 * | | | +-------------------------------- Writes Enabled
495 * | | +---------------------------------- Caching Enabled
496 * | +------------------------------------ Execution Prevented
497 * +--------------------------------------- BOOTCS
499 #define CONFIG_SYS_SC520_CAR_PAR 0x903d9200
501 /*-----------------------------------------------------------------------
502 * PAR for Low Level I/O (LEDs, Hex Switches etc) - 33 Bytes @ 0x1000, GPCS6
504 * 001 110 0 000100000 0001000000000000 }- 0x38201000
505 * \ / \ / | \---+---/ \------+-------/
506 * | | | | +----------- Start at 0x00001000
507 * | | | +------------------------ 33 Bytes (0x20 + 1)
508 * | | +------------------------------ Ignored
509 * | +--------------------------------- GPCS6
510 * +------------------------------------- GP Bus I/O
512 #define CONFIG_SYS_SC520_LLIO_PAR 0x38201000
514 /*-----------------------------------------------------------------------
515 * PAR for Compact Flash Port #1 - 4kB @ 0x200000000, CS5
516 * PAR for Compact Flash Port #2 - 4kB @ 0x200010000, CS7
518 * 010 101 0 0000000 100000000000000000 }- 0x54020000
519 * 010 111 0 0000000 100000000000000001 }- 0x5c020001
520 * \ / \ / | \--+--/ \-------+--------/
521 * | | | | +------------ Start at 0x200000000
522 * | | | | 0x200010000
523 * | | | +------------------------- 4kB Region Size
524 * | | | ((0 + 1) * 4kB)
525 * | | +------------------------------ 4k Page Size
526 * | +--------------------------------- GPCS5
528 * +------------------------------------- GP Bus Memory
530 #define CONFIG_SYS_SC520_CF1_PAR 0x54020000
531 #define CONFIG_SYS_SC520_CF2_PAR 0x5c020001
533 /*-----------------------------------------------------------------------
534 * PAR for Extra 16550 UART A - 8 bytes @ 0x013f8, GPCS0
535 * PAR for Extra 16550 UART B - 8 bytes @ 0x012f8, GPCS3
536 * PAR for Extra 16550 UART C - 8 bytes @ 0x011f8, GPCS4
537 * PAR for Extra 16550 UART D - 8 bytes @ 0x010f8, GPCS5
539 * 001 000 0 000000111 0001001111111000 }- 0x200713f8
540 * 001 011 0 000000111 0001001011111000 }- 0x2c0712f8
541 * 001 011 0 000000111 0001001011111000 }- 0x300711f8
542 * 001 011 0 000000111 0001001011111000 }- 0x340710f8
543 * \ / \ / | \---+---/ \------+-------/
544 * | | | | +----------- Start at 0x013f8
548 * | | | +------------------------ 33 Bytes (32 + 1)
549 * | | +------------------------------ Ignored
550 * | +--------------------------------- GPCS6
551 * +------------------------------------- GP Bus I/O
553 #define CONFIG_SYS_SC520_UARTA_PAR 0x200713f8
554 #define CONFIG_SYS_SC520_UARTB_PAR 0x2c0712f8
555 #define CONFIG_SYS_SC520_UARTC_PAR 0x300711f8
556 #define CONFIG_SYS_SC520_UARTD_PAR 0x340710f8
558 /*-----------------------------------------------------------------------
559 * PAR for StrataFlash #1 - 16MB @ 0x10000000, ROMCS1
560 * PAR for StrataFlash #2 - 16MB @ 0x11000000, ROMCS2
562 * 101 0 1 0 1 00011111111 01000000000000 }- 0xaa3fd000
563 * 110 0 1 0 1 00011111111 01000100000000 }- 0xca3fd100
564 * \ / | | | | \----+----/ \-----+------/
565 * | | | | | | +---------- Start at 0x10000000
566 * | | | | | | 0x11000000
567 * | | | | | +----------------------- 16MB Region Size
568 * | | | | | ((255 + 1) * 64kB)
569 * | | | | +------------------------------ 64kB Page Size
570 * | | | +-------------------------------- Writes Enabled
571 * | | +---------------------------------- Caching Disabled
572 * | +------------------------------------ Execution Enabled
573 * +--------------------------------------- ROMCS1
576 #define CONFIG_SYS_SC520_SF1_PAR 0xaa3fd000
577 #define CONFIG_SYS_SC520_SF2_PAR 0xca3fd100
579 /*-----------------------------------------------------------------------
580 * PAR for SRAM #1 - 1MB @ 0x19000000, GPCS0
581 * PAR for SRAM #2 - 1MB @ 0x19100000, GPCS3
583 * 010 000 1 00000001111 01100100000000 }- 0x4203d900
584 * 010 011 1 00000001111 01100100010000 }- 0x4e03d910
585 * \ / \ / | \----+----/ \-----+------/
586 * | | | | +---------- Start at 0x19000000
588 * | | | +----------------------- 1MB Region Size
589 * | | | ((15 + 1) * 64kB)
590 * | | +------------------------------ 64kB Page Size
591 * | +--------------------------------- GPCS0
593 * +------------------------------------- GP Bus Memory
595 #define CONFIG_SYS_SC520_SRAM1_PAR 0x4203d900
596 #define CONFIG_SYS_SC520_SRAM2_PAR 0x4e03d910
598 /*-----------------------------------------------------------------------
599 * PAR for Dual-Port RAM - 4kB @ 0x18100000, GPCS4
601 * 010 100 0 00000000 11000000100000000 }- 0x50018100
602 * \ / \ / | \---+--/ \-------+-------/
603 * | | | | +----------- Start at 0x18100000
604 * | | | +------------------------ 4kB Region Size
605 * | | | ((0 + 1) * 4kB)
606 * | | +------------------------------ 4kB Page Size
607 * | +--------------------------------- GPCS4
608 * +------------------------------------- GP Bus Memory
610 #define CONFIG_SYS_SC520_DPRAM_PAR 0x50018100
612 #endif /* __CONFIG_H */