3 * Graeme Russ, graeme.russ@gmail.com.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * board/config.h - configuration options, board specific
31 #define CONFIG_RELOC_FIXUP_WORKS
34 * Stuff still to be dealt with -
36 #define CONFIG_RTC_MC146818
39 * High Level Configuration Options
44 #define CONFIG_X86 1 /* Intel X86 CPU */
45 #define CONFIG_SYS_SC520 1 /* AMD SC520 */
46 #define CONFIG_SYS_SC520_SSI
47 #define CONFIG_SHOW_BOOT_PROGRESS 1
48 #define CONFIG_LAST_STAGE_INIT 1
51 * If CONFIG_HW_WATCHDOG is not defined, the watchdog jumper on the
52 * bottom (processor) board MUST be removed!
54 #undef CONFIG_WATCHDOG
55 #undef CONFIG_HW_WATCHDOG
57 /*-----------------------------------------------------------------------
60 #undef CONFIG_VIDEO /* No Video Hardware */
61 #undef CONFIG_CFB_CONSOLE
64 * Size of malloc() pool
66 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
68 #define CONFIG_BAUDRATE 9600
70 /*-----------------------------------------------------------------------
71 * Command line configuration.
73 #include <config_cmd_default.h>
75 #define CONFIG_CMD_BDI /* bdinfo */
76 #define CONFIG_CMD_BOOTD /* bootd */
77 #define CONFIG_CMD_CONSOLE /* coninfo */
78 #define CONFIG_CMD_ECHO /* echo arguments */
79 #define CONFIG_CMD_FLASH /* flinfo, erase, protect */
80 #define CONFIG_CMD_FPGA /* FPGA configuration Support */
81 #define CONFIG_CMD_IMI /* iminfo */
82 #define CONFIG_CMD_IMLS /* List all found images */
83 #define CONFIG_CMD_IRQ /* IRQ Information */
84 #define CONFIG_CMD_ITEST /* Integer (and string) test */
85 #define CONFIG_CMD_LOADB /* loadb */
86 #define CONFIG_CMD_LOADS /* loads */
87 #define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop mtest */
88 #define CONFIG_CMD_MISC /* Misc functions like sleep etc*/
89 #undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
90 #undef CONFIG_CMD_NFS /* NFS support */
91 #define CONFIG_CMD_PCI /* PCI support */
92 #define CONFIG_CMD_RUN /* run command in env variable */
93 #define CONFIG_CMD_SAVEENV /* saveenv */
94 #define CONFIG_CMD_SETGETDCR /* DCR support on 4xx */
95 #define CONFIG_CMD_SOURCE /* "source" command Support */
96 #define CONFIG_CMD_XIMG /* Load part of Multi Image */
98 #define CONFIG_BOOTDELAY 15
99 #define CONFIG_BOOTARGS "root=/dev/mtdblock0 console=ttyS0,9600"
100 /* #define CONFIG_BOOTCOMMAND "bootm 38000000" */
102 #if defined(CONFIG_CMD_KGDB)
103 #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
104 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
108 * Miscellaneous configurable options
110 #define CONFIG_SYS_LONGHELP /* undef to save memory */
111 #define CONFIG_SYS_PROMPT "boot > " /* Monitor Command Prompt */
112 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
113 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
114 sizeof(CONFIG_SYS_PROMPT) + \
115 16) /* Print Buffer Size */
116 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
117 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
119 #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
120 #define CONFIG_SYS_MEMTEST_END 0x01000000 /* 1 ... 16 MB in DRAM */
122 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
124 #define CONFIG_SYS_HZ 1024 /* incrementer freq: 1kHz */
126 /* valid baudrates */
127 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
129 /*-----------------------------------------------------------------------
130 * SDRAM Configuration
132 #define CONFIG_SYS_SDRAM_DRCTMCTL 0x18
133 #define CONFIG_NR_DRAM_BANKS 4
135 /* CONFIG_SYS_SDRAM_DRCTMCTL Overrides the following*/
136 #undef CONFIG_SYS_SDRAM_PRECHARGE_DELAY
137 #undef CONFIG_SYS_SDRAM_REFRESH_RATE
138 #undef CONFIG_SYS_SDRAM_RAS_CAS_DELAY
139 #undef CONFIG_SYS_SDRAM_CAS_LATENCY_2T
140 #undef CONFIG_SYS_SDRAM_CAS_LATENCY_3T
142 /*-----------------------------------------------------------------------
145 #define CONFIG_SYS_SC520_HIGH_SPEED 0 /* 100 or 133MHz */
146 #undef CONFIG_SYS_SC520_RESET /* use SC520 MMCR's to reset cpu */
147 #define CONFIG_SYS_SC520_TIMER /* use SC520 swtimers */
148 #undef CONFIG_SYS_GENERIC_TIMER /* use the i8254 PIT timers */
149 #undef CONFIG_SYS_TSC_TIMER /* use the Pentium TSC timers */
150 #define CONFIG_SYS_USE_SIO_UART 0 /* prefer the uarts on the SIO to those
151 * in the SC520 on the CDP */
152 #define CONFIG_SYS_PCAT_INTERRUPTS
153 #define CONFIG_SYS_NUM_IRQS 16
155 /*-----------------------------------------------------------------------
156 * Memory organization
158 #define CONFIG_SYS_STACK_SIZE 0x8000 /* Size of bootloader stack */
159 #define CONFIG_SYS_BL_START_FLASH 0x38040000 /* Address of relocated code */
160 #define CONFIG_SYS_BL_START_RAM 0x03fd0000 /* Address of relocated code */
161 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE
162 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
163 #define CONFIG_SYS_FLASH_BASE 0x38000000 /* Boot Flash */
164 #define CONFIG_SYS_FLASH_BASE_1 0x10000000 /* StrataFlash 1 */
165 #define CONFIG_SYS_FLASH_BASE_2 0x11000000 /* StrataFlash 2 */
167 /* timeout values are in ticks */
168 #define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
169 #define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Write */
171 /* allow to overwrite serial and ethaddr */
172 #define CONFIG_ENV_OVERWRITE
174 /*-----------------------------------------------------------------------
175 * FLASH configuration
177 #define CONFIG_FLASH_CFI_DRIVER /* Use the common driver */
178 #define CONFIG_FLASH_CFI_LEGACY
179 #define CONFIG_SYS_FLASH_CFI /* Flash is CFI conformant */
180 #define CONFIG_SYS_MAX_FLASH_BANKS 3 /* max number of memory banks */
181 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, \
182 CONFIG_SYS_FLASH_BASE_1, \
183 CONFIG_SYS_FLASH_BASE_2}
184 #define CONFIG_SYS_FLASH_EMPTY_INFO
185 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
186 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
187 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
188 #define CONFIG_SYS_FLASH_LEGACY_512Kx8
190 /*-----------------------------------------------------------------------
191 * Environment configuration
193 #define CONFIG_ENV_IS_IN_FLASH 1
194 #define CONFIG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */
195 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
196 #define CONFIG_ENV_ADDR CONFIG_SYS_FLASH_BASE_1
198 #define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE_1 + \
199 CONFIG_ENV_SECT_SIZE)
200 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SECT_SIZE
203 /*-----------------------------------------------------------------------
206 #define CONFIG_PCI /* include pci support */
207 #define CONFIG_PCI_PNP /* pci plug-and-play */
208 #define CONFIG_SYS_FIRST_PCI_IRQ 10
209 #define CONFIG_SYS_SECOND_PCI_IRQ 9
210 #define CONFIG_SYS_THIRD_PCI_IRQ 11
211 #define CONFIG_SYS_FORTH_PCI_IRQ 15
213 /*-----------------------------------------------------------------------
214 * Hardware watchdog configuration
216 #define CONFIG_SYS_WATCHDOG_PIO_BIT 0x8000
217 #define CONFIG_SYS_WATCHDIG_PIO_DATA SC520_PIODATA15_0
218 #define CONFIG_SYS_WATCHDIG_PIO_CLR SC520_PIOCLR15_0
219 #define CONFIG_SYS_WATCHDIG_PIO_SET SC520_PIOSET15_0
221 /*-----------------------------------------------------------------------
224 #define CONFIG_SYS_FPGA_PROGRAM_PIO_BIT 0x2000
225 #define CONFIG_SYS_FPGA_INIT_PIO_BIT 0x4000
226 #define CONFIG_SYS_FPGA_DONE_PIO_BIT 0x8000
227 #define CONFIG_SYS_FPGA_PIO_DATA SC520_PIODATA31_16
228 #define CONFIG_SYS_FPGA_PIO_DIRECTION SC520_PIODIR31_16
229 #define CONFIG_SYS_FPGA_PIO_CLR SC520_PIOCLR31_16
230 #define CONFIG_SYS_FPGA_PIO_SET SC520_PIOSET31_16
231 #define CONFIG_SYS_FPGA_PROGRAM_BIT_DROP_TIME 1 /* milliseconds */
232 #define CONFIG_SYS_FPGA_MAX_INIT_TIME 10 /* milliseconds */
233 #define CONFIG_SYS_FPGA_MAX_FINALISE_TIME 10 /* milliseconds */
234 #define CONFIG_SYS_FPGA_SSI_DATA_RATE 8333 /* kHz (33.3333MHz xtal) */
236 #ifndef __ASSEMBLER__
237 extern unsigned long ip;
239 #define PRINTIP asm ("call 0\n" \
244 : /* No Input Registers */ \
246 printf("IP: 0x%08lx (File: %s, Line: %d)\n", ip, __FILE__, __LINE__);
249 #endif /* __CONFIG_H */