2 * Configuation settings for the Renesas Solutions ECOVEC board
4 * Copyright (C) 2009 - 2011 Renesas Solutions Corp.
5 * Copyright (C) 2009 Kuninori Morimoto <morimoto.kuninori@renesas.com>
6 * Copyright (C) 2010, 2011 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
8 * SPDX-License-Identifier: GPL-2.0+
15 * Address Interface BusWidth
16 *-----------------------------------------
17 * 0x0000_0000 U-Boot 16bit
18 * 0x0004_0000 Linux romImage 16bit
19 * 0x0014_0000 MTD for Linux 16bit
20 * 0x0400_0000 Internal I/O 16/32bit
21 * 0x0800_0000 DRAM 32bit
22 * 0x1800_0000 MFI 16bit
26 #define CONFIG_CPU_SH7724 1
27 #define CONFIG_BOARD_LATE_INIT 1
28 #define CONFIG_ECOVEC 1
30 #define CONFIG_ECOVEC_ROMIMAGE_ADDR 0xA0040000
31 #define CONFIG_SYS_TEXT_BASE 0x8FFC0000
33 #define CONFIG_CMD_PING
34 #define CONFIG_CMD_MII
35 #define CONFIG_CMD_SDRAM
36 #define CONFIG_CMD_ENV
37 #define CONFIG_CMD_USB
38 #define CONFIG_CMD_FAT
39 #define CONFIG_CMD_EXT2
41 #define CONFIG_USB_STORAGE
42 #define CONFIG_DOS_PARTITION
44 #define CONFIG_BAUDRATE 115200
45 #define CONFIG_BOOTDELAY 3
46 #define CONFIG_BOOTARGS "console=ttySC0,115200"
48 #define CONFIG_VERSION_VARIABLE
49 #undef CONFIG_SHOW_BOOT_PROGRESS
52 #define CONFIG_CMD_I2C
53 #define CONFIG_SYS_I2C
54 #define CONFIG_SYS_I2C_SH
55 #define CONFIG_SYS_I2C_SLAVE 0x7F
56 #define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 2
57 #define CONFIG_SYS_I2C_SH_BASE0 0xA4470000
58 #define CONFIG_SYS_I2C_SH_SPEED0 100000
59 #define CONFIG_SYS_I2C_SH_BASE1 0xA4750000
60 #define CONFIG_SYS_I2C_SH_SPEED1 100000
61 #define CONFIG_SH_I2C_DATA_HIGH 4
62 #define CONFIG_SH_I2C_DATA_LOW 5
63 #define CONFIG_SH_I2C_CLOCK 41666666
66 #define CONFIG_SH_ETHER 1
67 #define CONFIG_SH_ETHER_USE_PORT (0)
68 #define CONFIG_SH_ETHER_PHY_ADDR (0x1f)
69 #define CONFIG_PHY_SMSC 1
71 #define CONFIG_BITBANGMII
72 #define CONFIG_BITBANGMII_MULTI
73 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
76 #define CONFIG_USB_R8A66597_HCD
77 #define CONFIG_R8A66597_BASE_ADDR 0xA4D80000
78 #define CONFIG_R8A66597_XTAL 0x0000 /* 12MHz */
79 #define CONFIG_R8A66597_LDRV 0x8000 /* 3.3V */
80 #define CONFIG_R8A66597_ENDIAN 0x0000 /* little */
81 #define CONFIG_SUPERH_ON_CHIP_R8A66597
83 /* undef to save memory */
84 #define CONFIG_SYS_LONGHELP
85 /* Monitor Command Prompt */
86 /* Buffer size for input from the Console */
87 #define CONFIG_SYS_CBSIZE 256
88 /* Buffer size for Console output */
89 #define CONFIG_SYS_PBSIZE 256
90 /* max args accepted for monitor commands */
91 #define CONFIG_SYS_MAXARGS 16
92 /* Buffer size for Boot Arguments passed to kernel */
93 #define CONFIG_SYS_BARGSIZE 512
94 /* List of legal baudrate settings for this board */
95 #define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
98 #define CONFIG_SCIF_CONSOLE 1
100 #define CONFIG_CONS_SCIF0 1
102 /* Suppress display of console information at boot */
103 #undef CONFIG_SYS_CONSOLE_INFO_QUIET
104 #undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
105 #undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
108 #define CONFIG_SYS_SDRAM_BASE (0x88000000)
109 #define CONFIG_SYS_SDRAM_SIZE (256 * 1024 * 1024)
110 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024)
112 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE)
113 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 200 * 1024 * 1024)
114 /* Enable alternate, more extensive, memory test */
115 #undef CONFIG_SYS_ALT_MEMTEST
116 /* Scratch address used by the alternate memory test */
117 #undef CONFIG_SYS_MEMTEST_SCRATCH
119 /* Enable temporary baudrate change while serial download */
120 #undef CONFIG_SYS_LOADS_BAUD_CHANGE
123 #define CONFIG_FLASH_CFI_DRIVER 1
124 #define CONFIG_SYS_FLASH_CFI
125 #undef CONFIG_SYS_FLASH_QUIET_TEST
126 #define CONFIG_SYS_FLASH_EMPTY_INFO
127 #define CONFIG_SYS_FLASH_BASE (0xA0000000)
128 #define CONFIG_SYS_MAX_FLASH_SECT 512
130 /* if you use all NOR Flash , you change dip-switch. Please see Manual. */
131 #define CONFIG_SYS_MAX_FLASH_BANKS 1
132 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
134 /* Timeout for Flash erase operations (in ms) */
135 #define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000)
136 /* Timeout for Flash write operations (in ms) */
137 #define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000)
138 /* Timeout for Flash set sector lock bit operations (in ms) */
139 #define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000)
140 /* Timeout for Flash clear lock bit operations (in ms) */
141 #define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000)
144 * Use hardware flash sectors protection instead
145 * of U-Boot software protection
147 #undef CONFIG_SYS_FLASH_PROTECTION
148 #undef CONFIG_SYS_DIRECT_FLASH_TFTP
150 /* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */
151 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE)
153 #define CONFIG_SYS_MONITOR_LEN (256 * 1024)
154 /* Size of DRAM reserved for malloc() use */
155 #define CONFIG_SYS_MALLOC_LEN (256 * 1024)
156 #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
159 #define CONFIG_ENV_IS_IN_FLASH
160 #define CONFIG_ENV_OVERWRITE 1
161 #define CONFIG_ENV_SECT_SIZE (128 * 1024)
162 #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
163 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
164 /* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
165 #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
166 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
169 #define CONFIG_SYS_CLK_FREQ 41666666
170 #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
171 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
172 #define CONFIG_SYS_TMU_CLK_DIV 4
174 #endif /* __ECOVEC_H */