3 * egnite GmbH <info@egnite.de>
5 * Configuation settings for Ethernut 5 with AT91SAM9XE.
7 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/hardware.h>
15 /* The first stage boot loader expects u-boot running at this address. */
16 #define CONFIG_SYS_TEXT_BASE 0x27000000 /* 16MB available */
18 /* The first stage boot loader takes care of low level initialization. */
19 #define CONFIG_SKIP_LOWLEVEL_INIT
21 /* Set our official architecture number. */
22 #define CONFIG_MACH_TYPE MACH_TYPE_ETHERNUT5
25 #define CONFIG_ARCH_CPU_INIT
27 /* ARM asynchronous clock */
28 #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
29 #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */
31 /* 32kB internal SRAM */
32 #define CONFIG_SRAM_BASE 0x00300000 /*AT91SAM9XE_SRAM_BASE */
33 #define CONFIG_SRAM_SIZE (32 << 10)
34 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SRAM_BASE + CONFIG_SRAM_SIZE - \
35 GENERATED_GBL_DATA_SIZE)
37 /* 128MB SDRAM in 1 bank */
38 #define CONFIG_NR_DRAM_BANKS 1
39 #define CONFIG_SYS_SDRAM_BASE 0x20000000
40 #define CONFIG_SYS_SDRAM_SIZE (128 << 20)
41 #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE
42 #define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
43 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20))
44 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
45 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE \
46 - CONFIG_SYS_MALLOC_LEN)
48 /* 512kB on-chip NOR flash */
49 # define CONFIG_SYS_MAX_FLASH_BANKS 1
50 # define CONFIG_SYS_FLASH_BASE 0x00200000 /* AT91SAM9XE_FLASH_BASE */
51 # define CONFIG_AT91_EFLASH
52 # define CONFIG_SYS_MAX_FLASH_SECT 32
53 # define CONFIG_SYS_FLASH_PROTECTION /* First stage loader in sector 0 */
54 # define CONFIG_EFLASH_PROTSECTORS 1
56 /* 512kB DataFlash at NPCS0 */
57 #define CONFIG_SYS_MAX_DATAFLASH_BANKS 1
58 #define CONFIG_HAS_DATAFLASH
59 #define CONFIG_ATMEL_DATAFLASH_SPI
60 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000
61 #define DATAFLASH_TCSS (0x1a << 16)
62 #define DATAFLASH_TCHS (0x1 << 24)
64 #define CONFIG_ENV_IS_IN_SPI_FLASH
65 #define CONFIG_ENV_OFFSET 0x3DE000
66 #define CONFIG_ENV_SECT_SIZE (132 << 10)
67 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
68 #define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 \
70 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 \
74 #define CONFIG_ATMEL_SPI
75 #define AT91_SPI_CLK 15000000
78 #define CONFIG_ATMEL_USART
79 #define CONFIG_USART3 /* USART 3 is DBGU */
80 #define CONFIG_BAUDRATE 115200
81 #define CONFIG_USART_BASE ATMEL_BASE_DBGU
82 #define CONFIG_USART_ID ATMEL_ID_SYS
84 /* Misc. hardware drivers */
85 #define CONFIG_AT91_GPIO
87 /* Command line configuration */
88 #define CONFIG_CMD_JFFS2
89 #define CONFIG_CMD_MTDPARTS
90 #define CONFIG_CMD_NAND
92 #ifndef MINIMAL_LOADER
93 #define CONFIG_CMD_BSP
94 #define CONFIG_CMD_DATE
95 #define CONFIG_CMD_REISER
96 #define CONFIG_CMD_SAVES
97 #define CONFIG_CMD_UBIFS
98 #define CONFIG_CMD_UNZIP
102 #ifdef CONFIG_CMD_NAND
103 #define CONFIG_SYS_MAX_NAND_DEVICE 1
104 #define CONFIG_SYS_NAND_BASE 0x40000000
105 #define CONFIG_SYS_NAND_DBW_8
106 #define CONFIG_NAND_ATMEL
107 /* our ALE is AD21 */
108 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
109 /* our CLE is AD22 */
110 #define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
111 #define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PC(14)
115 #ifdef CONFIG_CMD_JFFS2
116 #define CONFIG_JFFS2_CMDLINE
117 #define CONFIG_JFFS2_NAND
121 #define CONFIG_NET_RETRY_COUNT 20
124 #define CONFIG_PHY_ID 0
125 #define CONFIG_MACB_SEARCH_PHY
128 #ifdef CONFIG_CMD_MMC
129 #define CONFIG_GENERIC_ATMEL_MCI
130 #define CONFIG_SYS_MMC_CD_PIN AT91_PIO_PORTC, 8
134 #ifdef CONFIG_CMD_USB
135 #define CONFIG_USB_ATMEL
136 #define CONFIG_USB_ATMEL_CLK_SEL_PLLB
137 #define CONFIG_USB_OHCI_NEW
138 #define CONFIG_SYS_USB_OHCI_CPU_INIT
139 #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000
140 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "host"
141 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
145 #if defined(CONFIG_CMD_DATE) || defined(CONFIG_CMD_SNTP)
146 #define CONFIG_RTC_PCF8563
147 #define CONFIG_SYS_I2C_RTC_ADDR 0x51
151 #define CONFIG_SYS_MAX_I2C_BUS 1
153 #define CONFIG_SYS_I2C
154 #define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
155 #define CONFIG_SYS_I2C_SOFT_SPEED 100000
156 #define CONFIG_SYS_I2C_SOFT_SLAVE 0
158 #define I2C_SOFT_DECLARATIONS
160 #define GPIO_I2C_SCL AT91_PIO_PORTA, 24
161 #define GPIO_I2C_SDA AT91_PIO_PORTA, 23
164 at91_set_pio_periph(AT91_PIO_PORTA, 23, 0); \
165 at91_set_pio_multi_drive(AT91_PIO_PORTA, 23, 1); \
166 at91_set_pio_periph(AT91_PIO_PORTA, 24, 0); \
167 at91_set_pio_output(AT91_PIO_PORTA, 24, 0); \
168 at91_set_pio_multi_drive(AT91_PIO_PORTA, 24, 1); \
171 #define I2C_ACTIVE at91_set_pio_output(AT91_PIO_PORTA, 23, 0)
172 #define I2C_TRISTATE at91_set_pio_input(AT91_PIO_PORTA, 23, 0)
173 #define I2C_SCL(bit) at91_set_pio_value(AT91_PIO_PORTA, 24, bit)
174 #define I2C_SDA(bit) at91_set_pio_value(AT91_PIO_PORTA, 23, bit)
175 #define I2C_DELAY udelay(100)
176 #define I2C_READ at91_get_pio_value(AT91_PIO_PORTA, 23)
178 /* DHCP/BOOTP options */
179 #ifdef CONFIG_CMD_DHCP
180 #define CONFIG_BOOTP_BOOTFILESIZE
181 #define CONFIG_BOOTP_BOOTPATH
182 #define CONFIG_BOOTP_GATEWAY
183 #define CONFIG_BOOTP_HOSTNAME
184 #define CONFIG_SYS_AUTOLOAD "n"
188 #define CONFIG_MTD_DEVICE
189 #define CONFIG_MTD_PARTITIONS
190 #if defined(CONFIG_CMD_MTDPARTS) || defined(CONFIG_CMD_NAND)
191 #define MTDIDS_DEFAULT "nand0=atmel_nand"
192 #define MTDPARTS_DEFAULT "mtdparts=atmel_nand:-(root)"
195 #define CONFIG_RBTREE
198 #define CONFIG_CMDLINE_TAG
199 #define CONFIG_SETUP_MEMORY_TAGS
200 #define CONFIG_INITRD_TAG
201 #define CONFIG_BOOTCOMMAND "cp.b 0xC00C6000 ${loadaddr} 0x294000; bootm"
202 #if defined(CONFIG_CMD_NAND)
203 #define CONFIG_BOOTARGS "console=ttyS0,115200 " \
204 "root=/dev/mtdblock0 " \
206 " rw rootfstype=jffs2"
209 /* Misc. u-boot settings */
210 #define CONFIG_SYS_CBSIZE 256
211 #define CONFIG_SYS_MAXARGS 16
212 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + 16 \
213 + sizeof(CONFIG_SYS_PROMPT))
214 #define CONFIG_SYS_LONGHELP
215 #define CONFIG_CMDLINE_EDITING