3 * egnite GmbH <info@egnite.de>
5 * Configuation settings for Ethernut 5 with AT91SAM9XE.
7 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/hardware.h>
15 #define CONFIG_SYS_GENERIC_BOARD
17 /* The first stage boot loader expects u-boot running at this address. */
18 #define CONFIG_SYS_TEXT_BASE 0x27000000 /* 16MB available */
20 /* The first stage boot loader takes care of low level initialization. */
21 #define CONFIG_SKIP_LOWLEVEL_INIT
23 /* Set our official architecture number. */
24 #define MACH_TYPE_ETHERNUT5 1971
25 #define CONFIG_MACH_TYPE MACH_TYPE_ETHERNUT5
28 #define CONFIG_DISPLAY_CPUINFO /* Display at console. */
29 #define CONFIG_ARCH_CPU_INIT
31 /* ARM asynchronous clock */
32 #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
33 #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */
35 /* 32kB internal SRAM */
36 #define CONFIG_SRAM_BASE 0x00300000 /*AT91SAM9XE_SRAM_BASE */
37 #define CONFIG_SRAM_SIZE (32 << 10)
38 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SRAM_BASE + CONFIG_SRAM_SIZE - \
39 GENERATED_GBL_DATA_SIZE)
41 /* 128MB SDRAM in 1 bank */
42 #define CONFIG_NR_DRAM_BANKS 1
43 #define CONFIG_SYS_SDRAM_BASE 0x20000000
44 #define CONFIG_SYS_SDRAM_SIZE (128 << 20)
45 #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE
46 #define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
47 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20))
48 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
49 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE \
50 - CONFIG_SYS_MALLOC_LEN)
52 /* 512kB on-chip NOR flash */
53 # define CONFIG_SYS_MAX_FLASH_BANKS 1
54 # define CONFIG_SYS_FLASH_BASE 0x00200000 /* AT91SAM9XE_FLASH_BASE */
55 # define CONFIG_AT91_EFLASH
56 # define CONFIG_SYS_MAX_FLASH_SECT 32
57 # define CONFIG_SYS_FLASH_PROTECTION /* First stage loader in sector 0 */
58 # define CONFIG_EFLASH_PROTSECTORS 1
60 /* 512kB DataFlash at NPCS0 */
61 #define CONFIG_SYS_MAX_DATAFLASH_BANKS 1
62 #define CONFIG_HAS_DATAFLASH
63 #define CONFIG_SPI_FLASH
64 #define CONFIG_SPI_FLASH_ATMEL
65 #define CONFIG_ATMEL_DATAFLASH_SPI
66 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000
67 #define DATAFLASH_TCSS (0x1a << 16)
68 #define DATAFLASH_TCHS (0x1 << 24)
70 #define CONFIG_ENV_IS_IN_SPI_FLASH
71 #define CONFIG_ENV_OFFSET 0x3DE000
72 #define CONFIG_ENV_SECT_SIZE (132 << 10)
73 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
74 #define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 \
76 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 \
80 #define CONFIG_ATMEL_SPI
81 #define AT91_SPI_CLK 15000000
84 #define CONFIG_ATMEL_USART
85 #define CONFIG_USART3 /* USART 3 is DBGU */
86 #define CONFIG_BAUDRATE 115200
87 #define CONFIG_USART_BASE ATMEL_BASE_DBGU
88 #define CONFIG_USART_ID ATMEL_ID_SYS
90 /* Misc. hardware drivers */
91 #define CONFIG_AT91_GPIO
93 /* Command line configuration */
94 #include <config_cmd_default.h>
96 #undef CONFIG_CMD_FPGA
97 #undef CONFIG_CMD_LOADS
99 #define CONFIG_CMD_JFFS2
100 #define CONFIG_CMD_MII
101 #define CONFIG_CMD_MTDPARTS
102 #define CONFIG_CMD_NAND
103 #define CONFIG_CMD_SPI
105 #ifdef MINIMAL_LOADER
106 #undef CONFIG_CMD_CONSOLE
107 #undef CONFIG_CMD_EDITENV
108 #undef CONFIG_CMD_IMI
109 #undef CONFIG_CMD_ITEST
110 #undef CONFIG_CMD_IMLS
111 #undef CONFIG_CMD_LOADB
112 #undef CONFIG_CMD_LOADS
113 #undef CONFIG_CMD_NFS
114 #undef CONFIG_CMD_SETGETDCR
115 #undef CONFIG_CMD_XIMG
117 #define CONFIG_CMD_ASKENV
118 #define CONFIG_CMD_BSP
119 #define CONFIG_CMD_CACHE
120 #define CONFIG_CMD_CDP
121 #define CONFIG_CMD_DATE
122 #define CONFIG_CMD_DHCP
123 #define CONFIG_CMD_DNS
124 #define CONFIG_CMD_EXT2
125 #define CONFIG_CMD_FAT
126 #define CONFIG_CMD_I2C
127 #define CONFIG_CMD_MMC
128 #define CONFIG_CMD_PING
129 #define CONFIG_CMD_RARP
130 #define CONFIG_CMD_REISER
131 #define CONFIG_CMD_SAVES
132 #define CONFIG_CMD_SETEXPR
133 #define CONFIG_CMD_SF
134 #define CONFIG_CMD_SNTP
135 #define CONFIG_CMD_UBI
136 #define CONFIG_CMD_UBIFS
137 #define CONFIG_CMD_UNZIP
138 #define CONFIG_CMD_USB
142 #ifdef CONFIG_CMD_NAND
143 #define CONFIG_SYS_MAX_NAND_DEVICE 1
144 #define CONFIG_SYS_NAND_BASE 0x40000000
145 #define CONFIG_SYS_NAND_DBW_8
146 #define CONFIG_NAND_ATMEL
147 /* our ALE is AD21 */
148 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
149 /* our CLE is AD22 */
150 #define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
151 #define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PC(14)
155 #ifdef CONFIG_CMD_JFFS2
156 #define CONFIG_MTD_NAND_ECC_JFFS2
157 #define CONFIG_JFFS2_CMDLINE
158 #define CONFIG_JFFS2_NAND
162 #define CONFIG_NET_RETRY_COUNT 20
165 #define CONFIG_PHY_ID 0
166 #define CONFIG_MACB_SEARCH_PHY
169 #ifdef CONFIG_CMD_MMC
171 #define CONFIG_GENERIC_MMC
172 #define CONFIG_GENERIC_ATMEL_MCI
173 #define CONFIG_SYS_MMC_CD_PIN AT91_PIO_PORTC, 8
177 #ifdef CONFIG_CMD_USB
178 #define CONFIG_USB_ATMEL
179 #define CONFIG_USB_ATMEL_CLK_SEL_PLLB
180 #define CONFIG_USB_OHCI_NEW
181 #define CONFIG_SYS_USB_OHCI_CPU_INIT
182 #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000
183 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "host"
184 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
185 #define CONFIG_USB_STORAGE
189 #if defined(CONFIG_CMD_DATE) || defined(CONFIG_CMD_SNTP)
190 #define CONFIG_RTC_PCF8563
191 #define CONFIG_SYS_I2C_RTC_ADDR 0x51
195 #define CONFIG_SYS_MAX_I2C_BUS 1
197 #define CONFIG_SYS_I2C
198 #define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
199 #define CONFIG_SYS_I2C_SOFT_SPEED 100000
200 #define CONFIG_SYS_I2C_SOFT_SLAVE 0
202 #define I2C_SOFT_DECLARATIONS
204 #define GPIO_I2C_SCL AT91_PIO_PORTA, 24
205 #define GPIO_I2C_SDA AT91_PIO_PORTA, 23
208 at91_set_pio_periph(AT91_PIO_PORTA, 23, 0); \
209 at91_set_pio_multi_drive(AT91_PIO_PORTA, 23, 1); \
210 at91_set_pio_periph(AT91_PIO_PORTA, 24, 0); \
211 at91_set_pio_output(AT91_PIO_PORTA, 24, 0); \
212 at91_set_pio_multi_drive(AT91_PIO_PORTA, 24, 1); \
215 #define I2C_ACTIVE at91_set_pio_output(AT91_PIO_PORTA, 23, 0)
216 #define I2C_TRISTATE at91_set_pio_input(AT91_PIO_PORTA, 23, 0)
217 #define I2C_SCL(bit) at91_set_pio_value(AT91_PIO_PORTA, 24, bit)
218 #define I2C_SDA(bit) at91_set_pio_value(AT91_PIO_PORTA, 23, bit)
219 #define I2C_DELAY udelay(100)
220 #define I2C_READ at91_get_pio_value(AT91_PIO_PORTA, 23)
222 /* DHCP/BOOTP options */
223 #ifdef CONFIG_CMD_DHCP
224 #define CONFIG_BOOTP_BOOTFILESIZE
225 #define CONFIG_BOOTP_BOOTPATH
226 #define CONFIG_BOOTP_GATEWAY
227 #define CONFIG_BOOTP_HOSTNAME
228 #define CONFIG_SYS_AUTOLOAD "n"
232 #define CONFIG_MTD_DEVICE
233 #define CONFIG_MTD_PARTITIONS
234 #if defined(CONFIG_CMD_MTDPARTS) || defined(CONFIG_CMD_NAND)
235 #define MTDIDS_DEFAULT "nand0=atmel_nand"
236 #define MTDPARTS_DEFAULT "mtdparts=atmel_nand:-(root)"
238 #if defined(CONFIG_CMD_REISER) || defined(CONFIG_CMD_EXT2) || \
239 defined(CONFIG_CMD_USB) || defined(CONFIG_MMC)
240 #define CONFIG_DOS_PARTITION
243 #define CONFIG_RBTREE
246 #define CONFIG_BOOTDELAY 3
247 #define CONFIG_CMDLINE_TAG
248 #define CONFIG_SETUP_MEMORY_TAGS
249 #define CONFIG_INITRD_TAG
250 #define CONFIG_BOOTCOMMAND "cp.b 0xC00C6000 ${loadaddr} 0x294000; bootm"
251 #if defined(CONFIG_CMD_NAND)
252 #define CONFIG_BOOTARGS "console=ttyS0,115200 " \
253 "root=/dev/mtdblock0 " \
255 " rw rootfstype=jffs2"
258 /* Misc. u-boot settings */
259 #define CONFIG_SYS_PROMPT "U-Boot> "
260 #define CONFIG_SYS_HUSH_PARSER
261 #define CONFIG_SYS_CBSIZE 256
262 #define CONFIG_SYS_MAXARGS 16
263 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + 16 \
264 + sizeof(CONFIG_SYS_PROMPT))
265 #define CONFIG_SYS_LONGHELP
266 #define CONFIG_CMDLINE_EDITING