2 * Copyright (C) 2013 Samsung Electronics
4 * Configuration settings for the SAMSUNG EXYNOS5 board.
6 * SPDX-License-Identifier: GPL-2.0+
9 #ifndef __CONFIG_EXYNOS5_COMMON_H
10 #define __CONFIG_EXYNOS5_COMMON_H
12 #define CONFIG_EXYNOS5 /* Exynos5 Family */
14 #include "exynos-common.h"
16 #define CONFIG_EXYNOS_SPL
20 #define CONFIG_CMD_TRACE
21 #define CONFIG_TRACE_BUFFER_SIZE (16 << 20)
22 #define CONFIG_TRACE_EARLY_SIZE (8 << 20)
23 #define CONFIG_TRACE_EARLY
24 #define CONFIG_TRACE_EARLY_ADDR 0x50000000
27 /* Enable ACE acceleration for SHA1 and SHA256 */
28 #define CONFIG_EXYNOS_ACE_SHA
29 #define CONFIG_SHA_HW_ACCEL
31 /* Power Down Modes */
32 #define S5P_CHECK_SLEEP 0x00000BAD
33 #define S5P_CHECK_DIDLE 0xBAD00000
34 #define S5P_CHECK_LPA 0xABAD0000
36 /* Offset for inform registers */
37 #define INFORM0_OFFSET 0x800
38 #define INFORM1_OFFSET 0x804
39 #define INFORM2_OFFSET 0x808
40 #define INFORM3_OFFSET 0x80c
42 /* select serial console configuration */
43 #define CONFIG_BAUDRATE 115200
44 #define EXYNOS5_DEFAULT_UART_OFFSET 0x010000
45 #define CONFIG_SILENT_CONSOLE
46 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
47 #define CONFIG_CONSOLE_MUX
49 #define CONFIG_CMD_HASH
51 /* Thermal Management Unit */
52 #define CONFIG_EXYNOS_TMU
53 #define CONFIG_CMD_DTT
54 #define CONFIG_TMU_CMD_DTT
57 #define COPY_BL2_FNPTR_ADDR 0x02020030
58 #define CONFIG_SUPPORT_EMMC_BOOT
60 #define CONFIG_SPL_LIBCOMMON_SUPPORT
61 #define CONFIG_SPL_GPIO_SUPPORT
62 #define CONFIG_SPL_LIBGENERIC_SUPPORT
64 /* specific .lds file */
65 #define CONFIG_SPL_LDSCRIPT "board/samsung/common/exynos-uboot-spl.lds"
67 /* Boot Argument Buffer Size */
68 /* memtest works on */
69 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
70 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000)
71 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
75 #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
76 #define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE
77 #define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
78 #define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE
79 #define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
80 #define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE
81 #define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
82 #define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE
83 #define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
84 #define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE
85 #define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
86 #define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE
87 #define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
88 #define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE
89 #define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
90 #define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE
92 #define CONFIG_SYS_MONITOR_BASE 0x00000000
94 #define CONFIG_SYS_MMC_ENV_DEV 0
96 #define CONFIG_SECURE_BL1_ONLY
98 /* Secure FW size configuration */
99 #ifdef CONFIG_SECURE_BL1_ONLY
100 #define CONFIG_SEC_FW_SIZE (8 << 10) /* 8KB */
102 #define CONFIG_SEC_FW_SIZE 0
105 /* Configuration of BL1, BL2, ENV Blocks on mmc */
106 #define CONFIG_RES_BLOCK_SIZE (512)
107 #define CONFIG_BL1_SIZE (16 << 10) /*16 K reserved for BL1*/
108 #define CONFIG_BL2_SIZE (512UL << 10UL) /* 512 KB */
109 #define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */
111 #define CONFIG_BL1_OFFSET (CONFIG_RES_BLOCK_SIZE + CONFIG_SEC_FW_SIZE)
112 #define CONFIG_BL2_OFFSET (CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE)
114 /* U-Boot copy size from boot Media to DRAM.*/
115 #define BL2_START_OFFSET (CONFIG_BL2_OFFSET/512)
116 #define BL2_SIZE_BLOC_COUNT (CONFIG_BL2_SIZE/512)
118 #define EXYNOS_COPY_SPI_FNPTR_ADDR 0x02020058
119 #define SPI_FLASH_UBOOT_POS (CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE)
122 #define CONFIG_SYS_I2C_S3C24X0
123 #define CONFIG_SYS_I2C_S3C24X0_SPEED 100000 /* 100 Kbps */
124 #define CONFIG_SYS_I2C_S3C24X0_SLAVE 0x0
127 #ifdef CONFIG_SPI_FLASH
128 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
129 #define CONFIG_SF_DEFAULT_SPEED 50000000
132 #ifdef CONFIG_ENV_IS_IN_SPI_FLASH
133 #define CONFIG_ENV_SPI_MODE SPI_MODE_0
134 #define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
135 #define CONFIG_ENV_SPI_BUS 1
136 #define CONFIG_ENV_SPI_MAX_HZ 50000000
139 /* Ethernet Controllor Driver */
140 #ifdef CONFIG_CMD_NET
141 #define CONFIG_SMC911X
142 #define CONFIG_SMC911X_BASE 0x5000000
143 #define CONFIG_SMC911X_16_BIT
144 #define CONFIG_ENV_SROM_BANK 1
145 #endif /*CONFIG_CMD_NET*/
148 #define CONFIG_CMD_HASH
149 #define CONFIG_HASH_VERIFY
151 #define CONFIG_SHA256
153 /* Enable Time Command */
156 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
157 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
159 #define CONFIG_USB_HOST_ETHER
160 #define CONFIG_USB_ETHER_ASIX
161 #define CONFIG_USB_ETHER_SMSC95XX
162 #define CONFIG_USB_ETHER_RTL8152
165 #define CONFIG_USB_BOOTING
166 #define EXYNOS_COPY_USB_FNPTR_ADDR 0x02020070
167 #define EXYNOS_USB_SECONDARY_BOOT 0xfeed0002
168 #define EXYNOS_IRAM_SECONDARY_BASE 0x02020018
170 #define BOOT_TARGET_DEVICES(func) \
176 #include <config_distro_bootcmd.h>
178 #ifndef MEM_LAYOUT_ENV_SETTINGS
179 /* 2GB RAM, bootm size of 256M, load scripts after that */
180 #define MEM_LAYOUT_ENV_SETTINGS \
181 "bootm_size=0x10000000\0" \
182 "kernel_addr_r=0x42000000\0" \
183 "fdt_addr_r=0x43000000\0" \
184 "ramdisk_addr_r=0x43300000\0" \
185 "scriptaddr=0x50000000\0" \
186 "pxefile_addr_r=0x51000000\0"
189 #ifndef EXYNOS_DEVICE_SETTINGS
190 #define EXYNOS_DEVICE_SETTINGS \
196 #ifndef EXYNOS_FDTFILE_SETTING
197 #define EXYNOS_FDTFILE_SETTING
200 #define CONFIG_EXTRA_ENV_SETTINGS \
201 EXYNOS_DEVICE_SETTINGS \
202 EXYNOS_FDTFILE_SETTING \
203 MEM_LAYOUT_ENV_SETTINGS \
206 #endif /* __CONFIG_EXYNOS5_COMMON_H */