2 * Copyright (C) 2013 Samsung Electronics
4 * Configuration settings for the SAMSUNG EXYNOS5 board.
6 * SPDX-License-Identifier: GPL-2.0+
12 /* High Level Configuration Options */
13 #define CONFIG_SAMSUNG /* in a SAMSUNG core */
14 #define CONFIG_S5P /* S5P Family */
15 #define CONFIG_EXYNOS5 /* which is in a Exynos5 Family */
17 #include <asm/arch/cpu.h> /* get chip and board defs */
19 #define CONFIG_SYS_GENERIC_BOARD
20 #define CONFIG_ARCH_CPU_INIT
21 #define CONFIG_DISPLAY_CPUINFO
22 #define CONFIG_DISPLAY_BOARDINFO
23 #define CONFIG_BOARD_COMMON
24 #define CONFIG_ARCH_EARLY_INIT_R
25 #define CONFIG_EXYNOS_SPL
27 /* Enable fdt support for Exynos5250 */
28 #define CONFIG_OF_CONTROL
29 #define CONFIG_OF_SEPARATE
31 /* Allow tracing to be enabled */
33 #define CONFIG_CMD_TRACE
34 #define CONFIG_TRACE_BUFFER_SIZE (16 << 20)
35 #define CONFIG_TRACE_EARLY_SIZE (8 << 20)
36 #define CONFIG_TRACE_EARLY
37 #define CONFIG_TRACE_EARLY_ADDR 0x50000000
39 /* Keep L2 Cache Disabled */
40 #define CONFIG_SYS_DCACHE_OFF
41 #define CONFIG_SYS_CACHELINE_SIZE 64
43 /* Enable ACE acceleration for SHA1 and SHA256 */
44 #define CONFIG_EXYNOS_ACE_SHA
45 #define CONFIG_SHA_HW_ACCEL
47 /* input clock of PLL: SMDK5250 has 24MHz input clock */
48 #define CONFIG_SYS_CLK_FREQ 24000000
50 #define CONFIG_SETUP_MEMORY_TAGS
51 #define CONFIG_CMDLINE_TAG
52 #define CONFIG_INITRD_TAG
53 #define CONFIG_CMDLINE_EDITING
55 /* Power Down Modes */
56 #define S5P_CHECK_SLEEP 0x00000BAD
57 #define S5P_CHECK_DIDLE 0xBAD00000
58 #define S5P_CHECK_LPA 0xABAD0000
60 /* Offset for inform registers */
61 #define INFORM0_OFFSET 0x800
62 #define INFORM1_OFFSET 0x804
63 #define INFORM2_OFFSET 0x808
64 #define INFORM3_OFFSET 0x80c
66 /* Size of malloc() pool */
67 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (4 << 20))
69 /* select serial console configuration */
70 #define CONFIG_BAUDRATE 115200
71 #define EXYNOS5_DEFAULT_UART_OFFSET 0x010000
72 #define CONFIG_SILENT_CONSOLE
75 #define CONFIG_CROS_EC /* CROS_EC protocol */
76 #define CONFIG_CROS_EC_SPI /* Support CROS_EC over SPI */
77 #define CONFIG_CROS_EC_I2C /* Support CROS_EC over I2C */
78 #define CONFIG_CROS_EC_KEYB /* CROS_EC keyboard input */
79 #define CONFIG_CMD_CROS_EC
80 #define CONFIG_KEYBOARD
82 /* Console configuration */
83 #define CONFIG_CONSOLE_MUX
84 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
85 #define EXYNOS_DEVICE_SETTINGS \
86 "stdin=serial,cros-ec-keyb\0" \
87 "stdout=serial,lcd\0" \
90 #define CONFIG_EXTRA_ENV_SETTINGS \
91 EXYNOS_DEVICE_SETTINGS
93 /* SD/MMC configuration */
94 #define CONFIG_GENERIC_MMC
97 #define CONFIG_S5P_SDHCI
99 #define CONFIG_EXYNOS_DWMMC
100 #define CONFIG_SUPPORT_EMMC_BOOT
101 #define CONFIG_BOUNCE_BUFFER
103 #define CONFIG_BOARD_EARLY_INIT_F
104 #define CONFIG_SKIP_LOWLEVEL_INIT
109 /* allow to overwrite serial and ethaddr */
110 #define CONFIG_ENV_OVERWRITE
112 /* Command definition*/
113 #include <config_cmd_default.h>
115 #define CONFIG_CMD_PING
116 #define CONFIG_CMD_ELF
117 #define CONFIG_CMD_MMC
118 #define CONFIG_CMD_EXT2
119 #define CONFIG_CMD_FAT
120 #define CONFIG_CMD_NET
121 #define CONFIG_CMD_HASH
123 #define CONFIG_BOOTDELAY 3
124 #define CONFIG_ZERO_BOOTDELAY_CHECK
126 /* Thermal Management Unit */
127 #define CONFIG_EXYNOS_TMU
128 #define CONFIG_CMD_DTT
129 #define CONFIG_TMU_CMD_DTT
133 #define CONFIG_CMD_TPM
134 #define CONFIG_TPM_TIS_I2C
135 #define CONFIG_TPM_TIS_I2C_BUS_NUMBER 3
136 #define CONFIG_TPM_TIS_I2C_SLAVE_ADDR 0x20
139 #define COPY_BL2_FNPTR_ADDR 0x02020030
141 #define CONFIG_SPL_LIBCOMMON_SUPPORT
142 #define CONFIG_SPL_GPIO_SUPPORT
144 /* specific .lds file */
145 #define CONFIG_SPL_LDSCRIPT "board/samsung/common/exynos-uboot-spl.lds"
147 /* Miscellaneous configurable options */
148 #define CONFIG_SYS_LONGHELP /* undef to save memory */
149 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
150 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
151 #define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */
152 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
153 #define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
154 /* Boot Argument Buffer Size */
155 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
156 /* memtest works on */
157 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
158 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000)
159 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
161 #define CONFIG_RD_LVL
163 #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
164 #define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE
165 #define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
166 #define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE
167 #define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
168 #define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE
169 #define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
170 #define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE
171 #define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
172 #define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE
173 #define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
174 #define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE
175 #define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
176 #define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE
177 #define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
178 #define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE
180 #define CONFIG_SYS_MONITOR_BASE 0x00000000
182 /* FLASH and environment organization */
183 #define CONFIG_SYS_NO_FLASH
184 #undef CONFIG_CMD_IMLS
186 #define CONFIG_SYS_MMC_ENV_DEV 0
188 #define CONFIG_SECURE_BL1_ONLY
190 /* Secure FW size configuration */
191 #ifdef CONFIG_SECURE_BL1_ONLY
192 #define CONFIG_SEC_FW_SIZE (8 << 10) /* 8KB */
194 #define CONFIG_SEC_FW_SIZE 0
197 /* Configuration of BL1, BL2, ENV Blocks on mmc */
198 #define CONFIG_RES_BLOCK_SIZE (512)
199 #define CONFIG_BL1_SIZE (16 << 10) /*16 K reserved for BL1*/
200 #define CONFIG_BL2_SIZE (512UL << 10UL) /* 512 KB */
201 #define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */
203 #define CONFIG_BL1_OFFSET (CONFIG_RES_BLOCK_SIZE + CONFIG_SEC_FW_SIZE)
204 #define CONFIG_BL2_OFFSET (CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE)
206 /* Store environment at the end of a 4 MB SPI flash */
207 #define FLASH_SIZE (0x4 << 20)
208 #define CONFIG_ENV_OFFSET (FLASH_SIZE - CONFIG_BL2_SIZE)
210 /* U-boot copy size from boot Media to DRAM.*/
211 #define BL2_START_OFFSET (CONFIG_BL2_OFFSET/512)
212 #define BL2_SIZE_BLOC_COUNT (CONFIG_BL2_SIZE/512)
214 #define CONFIG_SPI_BOOTING
215 #define EXYNOS_COPY_SPI_FNPTR_ADDR 0x02020058
216 #define SPI_FLASH_UBOOT_POS (CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE)
218 #define CONFIG_DOS_PARTITION
219 #define CONFIG_EFI_PARTITION
220 #define CONFIG_CMD_PART
221 #define CONFIG_PARTITION_UUIDS
224 #define CONFIG_SYS_I2C_INIT_BOARD
225 #define CONFIG_SYS_I2C
226 #define CONFIG_CMD_I2C
227 #define CONFIG_SYS_I2C_S3C24X0_SPEED 100000 /* 100 Kbps */
228 #define CONFIG_SYS_I2C_S3C24X0
229 #define CONFIG_I2C_MULTI_BUS
230 #define CONFIG_SYS_I2C_S3C24X0_SLAVE 0x0
231 #define CONFIG_I2C_EDID
234 #define CONFIG_ENV_IS_IN_SPI_FLASH
235 #define CONFIG_SPI_FLASH
236 #define CONFIG_ENV_SPI_BASE 0x12D30000
238 #ifdef CONFIG_SPI_FLASH
239 #define CONFIG_EXYNOS_SPI
240 #define CONFIG_CMD_SF
241 #define CONFIG_CMD_SPI
242 #define CONFIG_SPI_FLASH_WINBOND
243 #define CONFIG_SPI_FLASH_GIGADEVICE
244 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
245 #define CONFIG_SF_DEFAULT_SPEED 50000000
246 #define EXYNOS5_SPI_NUM_CONTROLLERS 5
247 #define CONFIG_OF_SPI
250 #ifdef CONFIG_ENV_IS_IN_SPI_FLASH
251 #define CONFIG_ENV_SPI_MODE SPI_MODE_0
252 #define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
253 #define CONFIG_ENV_SPI_BUS 1
254 #define CONFIG_ENV_SPI_MAX_HZ 50000000
259 #define CONFIG_POWER_I2C
260 #define CONFIG_POWER_TPS65090
262 /* Ethernet Controllor Driver */
263 #ifdef CONFIG_CMD_NET
264 #define CONFIG_SMC911X
265 #define CONFIG_SMC911X_BASE 0x5000000
266 #define CONFIG_SMC911X_16_BIT
267 #define CONFIG_ENV_SROM_BANK 1
268 #endif /*CONFIG_CMD_NET*/
270 /* Enable PXE Support */
271 #ifdef CONFIG_CMD_NET
272 #define CONFIG_CMD_PXE
276 /* Enable devicetree support */
277 #define CONFIG_OF_LIBFDT
280 #define CONFIG_CMD_HASH
281 #define CONFIG_HASH_VERIFY
283 #define CONFIG_SHA256
285 /* Enable Time Command */
286 #define CONFIG_CMD_TIME
288 #define CONFIG_CMD_BOOTZ
290 #define CONFIG_CMD_GPIO
293 #define CONFIG_USB_BOOTING
294 #define EXYNOS_COPY_USB_FNPTR_ADDR 0x02020070
295 #define EXYNOS_USB_SECONDARY_BOOT 0xfeed0002
296 #define EXYNOS_IRAM_SECONDARY_BASE 0x02020018
298 #endif /* __CONFIG_H */