2 * Copyright (C) 2013 Samsung Electronics
4 * Configuration settings for the SAMSUNG EXYNOS5 board.
6 * SPDX-License-Identifier: GPL-2.0+
12 /* High Level Configuration Options */
13 #define CONFIG_SAMSUNG /* in a SAMSUNG core */
14 #define CONFIG_S5P /* S5P Family */
15 #define CONFIG_EXYNOS5 /* which is in a Exynos5 Family */
17 #include <asm/arch/cpu.h> /* get chip and board defs */
19 #define CONFIG_SYS_GENERIC_BOARD
20 #define CONFIG_ARCH_CPU_INIT
21 #define CONFIG_DISPLAY_CPUINFO
22 #define CONFIG_DISPLAY_BOARDINFO
23 #define CONFIG_BOARD_COMMON
24 #define CONFIG_ARCH_EARLY_INIT_R
25 #define CONFIG_EXYNOS_SPL
27 /* Enable fdt support for Exynos5250 */
28 #define CONFIG_OF_CONTROL
29 #define CONFIG_OF_SEPARATE
31 /* Allow tracing to be enabled */
33 #define CONFIG_CMD_TRACE
34 #define CONFIG_TRACE_BUFFER_SIZE (16 << 20)
35 #define CONFIG_TRACE_EARLY_SIZE (8 << 20)
36 #define CONFIG_TRACE_EARLY
37 #define CONFIG_TRACE_EARLY_ADDR 0x50000000
39 /* Keep L2 Cache Disabled */
40 #define CONFIG_SYS_DCACHE_OFF
41 #define CONFIG_SYS_CACHELINE_SIZE 64
43 /* Enable ACE acceleration for SHA1 and SHA256 */
44 #define CONFIG_EXYNOS_ACE_SHA
45 #define CONFIG_SHA_HW_ACCEL
47 /* input clock of PLL: SMDK5250 has 24MHz input clock */
48 #define CONFIG_SYS_CLK_FREQ 24000000
50 #define CONFIG_SETUP_MEMORY_TAGS
51 #define CONFIG_CMDLINE_TAG
52 #define CONFIG_INITRD_TAG
53 #define CONFIG_CMDLINE_EDITING
55 /* Power Down Modes */
56 #define S5P_CHECK_SLEEP 0x00000BAD
57 #define S5P_CHECK_DIDLE 0xBAD00000
58 #define S5P_CHECK_LPA 0xABAD0000
60 /* Offset for inform registers */
61 #define INFORM0_OFFSET 0x800
62 #define INFORM1_OFFSET 0x804
63 #define INFORM2_OFFSET 0x808
64 #define INFORM3_OFFSET 0x80c
66 /* Size of malloc() pool */
67 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (4 << 20))
69 /* select serial console configuration */
70 #define CONFIG_BAUDRATE 115200
71 #define EXYNOS5_DEFAULT_UART_OFFSET 0x010000
72 #define CONFIG_SILENT_CONSOLE
75 #define CONFIG_CROS_EC /* CROS_EC protocol */
76 #define CONFIG_CROS_EC_SPI /* Support CROS_EC over SPI */
77 #define CONFIG_CROS_EC_I2C /* Support CROS_EC over I2C */
78 #define CONFIG_CROS_EC_KEYB /* CROS_EC keyboard input */
79 #define CONFIG_CMD_CROS_EC
80 #define CONFIG_KEYBOARD
82 /* Console configuration */
83 #define CONFIG_CONSOLE_MUX
84 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
85 #define EXYNOS_DEVICE_SETTINGS \
86 "stdin=serial,cros-ec-keyb\0" \
87 "stdout=serial,lcd\0" \
90 #define CONFIG_EXTRA_ENV_SETTINGS \
91 EXYNOS_DEVICE_SETTINGS
93 /* SD/MMC configuration */
94 #define CONFIG_GENERIC_MMC
97 #define CONFIG_S5P_SDHCI
99 #define CONFIG_EXYNOS_DWMMC
100 #define CONFIG_SUPPORT_EMMC_BOOT
101 #define CONFIG_BOUNCE_BUFFER
103 #define CONFIG_BOARD_EARLY_INIT_F
104 #define CONFIG_SKIP_LOWLEVEL_INIT
109 /* allow to overwrite serial and ethaddr */
110 #define CONFIG_ENV_OVERWRITE
112 /* Command definition*/
113 #include <config_cmd_default.h>
115 #define CONFIG_CMD_PING
116 #define CONFIG_CMD_ELF
117 #define CONFIG_CMD_MMC
118 #define CONFIG_CMD_EXT2
119 #define CONFIG_CMD_FAT
120 #define CONFIG_CMD_NET
121 #define CONFIG_CMD_HASH
123 #define CONFIG_BOOTDELAY 3
124 #define CONFIG_ZERO_BOOTDELAY_CHECK
126 /* Thermal Management Unit */
127 #define CONFIG_EXYNOS_TMU
128 #define CONFIG_CMD_DTT
129 #define CONFIG_TMU_CMD_DTT
133 #define CONFIG_CMD_TPM
134 #define CONFIG_TPM_TIS_I2C
135 #define CONFIG_TPM_TIS_I2C_BUS_NUMBER 3
136 #define CONFIG_TPM_TIS_I2C_SLAVE_ADDR 0x20
140 #define COPY_BL2_FNPTR_ADDR 0x02020030
142 #define CONFIG_SPL_LIBCOMMON_SUPPORT
143 #define CONFIG_SPL_GPIO_SUPPORT
145 /* specific .lds file */
146 #define CONFIG_SPL_LDSCRIPT "board/samsung/common/exynos-uboot-spl.lds"
148 /* Miscellaneous configurable options */
149 #define CONFIG_SYS_LONGHELP /* undef to save memory */
150 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
151 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
152 #define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */
153 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
154 #define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
155 /* Boot Argument Buffer Size */
156 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
157 /* memtest works on */
158 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
159 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000)
160 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
162 #define CONFIG_RD_LVL
164 #define CONFIG_NR_DRAM_BANKS 8
165 #define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */
166 #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
167 #define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE
168 #define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
169 #define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE
170 #define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
171 #define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE
172 #define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
173 #define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE
174 #define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
175 #define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE
176 #define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
177 #define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE
178 #define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
179 #define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE
180 #define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
181 #define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE
183 #define CONFIG_SYS_MONITOR_BASE 0x00000000
185 /* FLASH and environment organization */
186 #define CONFIG_SYS_NO_FLASH
187 #undef CONFIG_CMD_IMLS
189 #define CONFIG_SYS_MMC_ENV_DEV 0
191 #define CONFIG_SECURE_BL1_ONLY
193 /* Secure FW size configuration */
194 #ifdef CONFIG_SECURE_BL1_ONLY
195 #define CONFIG_SEC_FW_SIZE (8 << 10) /* 8KB */
197 #define CONFIG_SEC_FW_SIZE 0
200 /* Configuration of BL1, BL2, ENV Blocks on mmc */
201 #define CONFIG_RES_BLOCK_SIZE (512)
202 #define CONFIG_BL1_SIZE (16 << 10) /*16 K reserved for BL1*/
203 #define CONFIG_BL2_SIZE (512UL << 10UL) /* 512 KB */
204 #define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */
206 #define CONFIG_BL1_OFFSET (CONFIG_RES_BLOCK_SIZE + CONFIG_SEC_FW_SIZE)
207 #define CONFIG_BL2_OFFSET (CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE)
209 /* Store environment at the end of a 4 MB SPI flash */
210 #define FLASH_SIZE (0x4 << 20)
211 #define CONFIG_ENV_OFFSET (FLASH_SIZE - CONFIG_BL2_SIZE)
213 /* U-boot copy size from boot Media to DRAM.*/
214 #define BL2_START_OFFSET (CONFIG_BL2_OFFSET/512)
215 #define BL2_SIZE_BLOC_COUNT (CONFIG_BL2_SIZE/512)
217 #define CONFIG_SPI_BOOTING
218 #define EXYNOS_COPY_SPI_FNPTR_ADDR 0x02020058
219 #define SPI_FLASH_UBOOT_POS (CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE)
221 #define CONFIG_DOS_PARTITION
222 #define CONFIG_EFI_PARTITION
223 #define CONFIG_CMD_PART
224 #define CONFIG_PARTITION_UUIDS
227 #define CONFIG_SYS_I2C_INIT_BOARD
228 #define CONFIG_SYS_I2C
229 #define CONFIG_CMD_I2C
230 #define CONFIG_SYS_I2C_S3C24X0_SPEED 100000 /* 100 Kbps */
231 #define CONFIG_SYS_I2C_S3C24X0
232 #define CONFIG_I2C_MULTI_BUS
233 #define CONFIG_SYS_I2C_S3C24X0_SLAVE 0x0
234 #define CONFIG_I2C_EDID
237 #define CONFIG_ENV_IS_IN_SPI_FLASH
238 #define CONFIG_SPI_FLASH
239 #define CONFIG_ENV_SPI_BASE 0x12D30000
241 #ifdef CONFIG_SPI_FLASH
242 #define CONFIG_EXYNOS_SPI
243 #define CONFIG_CMD_SF
244 #define CONFIG_CMD_SPI
245 #define CONFIG_SPI_FLASH_WINBOND
246 #define CONFIG_SPI_FLASH_GIGADEVICE
247 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
248 #define CONFIG_SF_DEFAULT_SPEED 50000000
249 #define EXYNOS5_SPI_NUM_CONTROLLERS 5
250 #define CONFIG_OF_SPI
253 #ifdef CONFIG_ENV_IS_IN_SPI_FLASH
254 #define CONFIG_ENV_SPI_MODE SPI_MODE_0
255 #define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
256 #define CONFIG_ENV_SPI_BUS 1
257 #define CONFIG_ENV_SPI_MAX_HZ 50000000
262 #define CONFIG_POWER_I2C
263 #define CONFIG_POWER_TPS65090
265 /* Ethernet Controllor Driver */
266 #ifdef CONFIG_CMD_NET
267 #define CONFIG_SMC911X
268 #define CONFIG_SMC911X_BASE 0x5000000
269 #define CONFIG_SMC911X_16_BIT
270 #define CONFIG_ENV_SROM_BANK 1
271 #endif /*CONFIG_CMD_NET*/
273 /* Enable PXE Support */
274 #ifdef CONFIG_CMD_NET
275 #define CONFIG_CMD_PXE
279 /* Enable devicetree support */
280 #define CONFIG_OF_LIBFDT
283 #define CONFIG_CMD_HASH
284 #define CONFIG_HASH_VERIFY
286 #define CONFIG_SHA256
288 /* Enable Time Command */
289 #define CONFIG_CMD_TIME
291 #define CONFIG_CMD_BOOTZ
293 #define CONFIG_CMD_GPIO
295 #endif /* __CONFIG_H */