git.sur5r.net Git - u-boot/blob - include/configs/ge_bx50v3.h

   1 /*
   2  * Copyright (C) 2015 Timesys Corporation
   3  * Copyright (C) 2015 General Electric Company
   4  * Copyright (C) 2014 Advantech
   5  * Copyright (C) 2012 Freescale Semiconductor, Inc.
   6  *
   7  * Configuration settings for the GE MX6Q Bx50v3 boards.
   8  *
   9  * SPDX-License-Identifier:     GPL-2.0+
  10  */
  11
  12 #ifndef __GE_BX50V3_CONFIG_H
  13 #define __GE_BX50V3_CONFIG_H
  14
  15 #include <asm/arch/imx-regs.h>
  16 #include <asm/mach-imx/gpio.h>
  17
  18 #define BX50V3_BOOTARGS_EXTRA
  19 #if defined(CONFIG_TARGET_GE_B450V3)
  20 #define CONFIG_BOARD_NAME       "General Electric B450v3"
  21 #elif defined(CONFIG_TARGET_GE_B650V3)
  22 #define CONFIG_BOARD_NAME       "General Electric B650v3"
  23 #elif defined(CONFIG_TARGET_GE_B850V3)
  24 #define CONFIG_BOARD_NAME       "General Electric B850v3"
  25 #undef BX50V3_BOOTARGS_EXTRA
  26 #define BX50V3_BOOTARGS_EXTRA   "video=DP-1:1024x768@60 " \
  27                                 "video=HDMI-A-1:1024x768@60 "
  28 #else
  29 #define CONFIG_BOARD_NAME       "General Electric BA16 Generic"
  30 #endif
  31
  32 #define CONFIG_MXC_UART_BASE    UART3_BASE
  33 #define CONSOLE_DEV     "ttymxc2"
  34
  35 #define CONFIG_SUPPORT_EMMC_BOOT
  36
  37
  38 #include "mx6_common.h"
  39 #include <linux/sizes.h>
  40
  41 #define CONFIG_CMDLINE_TAG
  42 #define CONFIG_SETUP_MEMORY_TAGS
  43 #define CONFIG_INITRD_TAG
  44 #define CONFIG_REVISION_TAG
  45 #define CONFIG_SYS_MALLOC_LEN           (10 * SZ_1M)
  46
  47 #define CONFIG_HW_WATCHDOG
  48 #define CONFIG_IMX_WATCHDOG
  49 #define CONFIG_WATCHDOG_TIMEOUT_MSECS 6000
  50
  51 #define CONFIG_MXC_UART
  52
  53 #define CONFIG_MXC_OCOTP
  54
  55 /* SATA Configs */
  56 #ifdef CONFIG_CMD_SATA
  57 #define CONFIG_SYS_SATA_MAX_DEVICE      1
  58 #define CONFIG_DWC_AHSATA_PORT_ID       0
  59 #define CONFIG_DWC_AHSATA_BASE_ADDR     SATA_ARB_BASE_ADDR
  60 #define CONFIG_LBA48
  61 #endif
  62
  63 /* MMC Configs */
  64 #define CONFIG_FSL_USDHC
  65 #define CONFIG_SYS_FSL_ESDHC_ADDR      0
  66 #define CONFIG_BOUNCE_BUFFER
  67
  68 /* USB Configs */
  69 #ifdef CONFIG_USB
  70 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
  71 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  72 #define CONFIG_MXC_USB_PORTSC   (PORT_PTS_UTMI | PORT_PTS_PTW)
  73 #define CONFIG_MXC_USB_FLAGS    0
  74
  75 #define CONFIG_USBD_HS
  76 #define CONFIG_USB_GADGET_MASS_STORAGE
  77 #endif
  78
  79 /* Networking Configs */
  80 #ifdef CONFIG_NET
  81 #define CONFIG_FEC_MXC
  82 #define CONFIG_MII
  83 #define IMX_FEC_BASE                    ENET_BASE_ADDR
  84 #define CONFIG_FEC_XCV_TYPE             RGMII
  85 #define CONFIG_ETHPRIME         "FEC"
  86 #define CONFIG_FEC_MXC_PHYADDR          4
  87 #define CONFIG_PHY_ATHEROS
  88 #endif
  89
  90 /* Serial Flash */
  91 #ifdef CONFIG_CMD_SF
  92 #define CONFIG_SF_DEFAULT_BUS           0
  93 #define CONFIG_SF_DEFAULT_CS            0
  94 #define CONFIG_SF_DEFAULT_SPEED 20000000
  95 #define CONFIG_SF_DEFAULT_MODE          SPI_MODE_0
  96 #endif
  97
  98 /* allow to overwrite serial and ethaddr */
  99 #define CONFIG_ENV_OVERWRITE
 100
 101 #define CONFIG_LOADADDR 0x12000000
 102
 103 #define CONFIG_EXTRA_ENV_SETTINGS \
 104         "bootcause=POR\0" \
 105         "bootlimit=10\0" \
 106         "image=/boot/fitImage\0" \
 107         "fdt_high=0xffffffff\0" \
 108         "dev=mmc\0" \
 109         "devnum=1\0" \
 110         "rootdev=mmcblk0p\0" \
 111         "quiet=quiet loglevel=0\0" \
 112         "console=" CONSOLE_DEV "\0" \
 113         "setargs=setenv bootargs root=/dev/${rootdev}${partnum} " \
 114                 "ro rootwait cma=128M " \
 115                 "bootcause=${bootcause} " \
 116                 "${quiet} console=${console} ${rtc_status} " \
 117                 BX50V3_BOOTARGS_EXTRA "\0" \
 118         "doquiet=" \
 119                 "if ext2load ${dev} ${devnum}:5 0x7000A000 /boot/console; " \
 120                         "then setenv quiet; fi\0" \
 121         "hasfirstboot=" \
 122                 "ext2load ${dev} ${devnum}:${partnum} 0x7000A000 " \
 123                 "/boot/bootcause/firstboot\0" \
 124         "swappartitions=" \
 125                 "setexpr partnum 3 - ${partnum}\0" \
 126         "failbootcmd=" \
 127                 "bx50_backlight_enable; " \
 128                 "msg=\"Monitor failed to start.  Try again, or contact GE Service for support.\"; " \
 129                 "echo $msg; " \
 130                 "setenv stdout vga; " \
 131                 "echo \"\n\n\n\n    \" $msg; " \
 132                 "setenv stdout serial; " \
 133                 "mw.b 0x7000A000 0xbc; " \
 134                 "mw.b 0x7000A001 0x00; " \
 135                 "ext4write ${dev} ${devnum}:5 0x7000A000 /boot/failures 2\0" \
 136         "altbootcmd=" \
 137                 "run doquiet; " \
 138                 "setenv partnum 1; run hasfirstboot || setenv partnum 2; " \
 139                 "run hasfirstboot || setenv partnum 0; " \
 140                 "if test ${partnum} != 0; then " \
 141                         "setenv bootcause REVERT; " \
 142                         "run swappartitions loadimage doboot; " \
 143                 "fi; " \
 144                 "run failbootcmd\0" \
 145         "loadimage=" \
 146                 "ext2load ${dev} ${devnum}:${partnum} ${loadaddr} ${image}\0" \
 147         "doboot=" \
 148                 "echo Booting from ${dev}:${devnum}:${partnum} ...; " \
 149                 "run setargs; " \
 150                 "bootm ${loadaddr}#conf@${confidx}\0" \
 151         "tryboot=" \
 152                 "setenv partnum 1; run hasfirstboot || setenv partnum 2; " \
 153                 "run loadimage || run swappartitions && run loadimage || " \
 154                 "setenv partnum 0 && echo MISSING IMAGE;" \
 155                 "run doboot; " \
 156                 "run failbootcmd\0" \
 157
 158 #define CONFIG_MMCBOOTCOMMAND \
 159         "if mmc dev ${devnum}; then " \
 160                 "run doquiet; " \
 161                 "run tryboot; " \
 162         "fi; " \
 163
 164 #define CONFIG_USBBOOTCOMMAND \
 165         "echo Unsupported; " \
 166
 167 #ifdef CONFIG_CMD_USB
 168 #define CONFIG_BOOTCOMMAND CONFIG_USBBOOTCOMMAND
 169 #else
 170 #define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND
 171 #endif
 172
 173 #define CONFIG_ARP_TIMEOUT     200UL
 174
 175 /* Miscellaneous configurable options */
 176
 177 #define CONFIG_SYS_MEMTEST_START       0x10000000
 178 #define CONFIG_SYS_MEMTEST_END         0x10010000
 179 #define CONFIG_SYS_MEMTEST_SCRATCH     0x10800000
 180
 181 #define CONFIG_SYS_LOAD_ADDR           CONFIG_LOADADDR
 182
 183 /* Physical Memory Map */
 184 #define CONFIG_NR_DRAM_BANKS           1
 185 #define PHYS_SDRAM                     MMDC0_ARB_BASE_ADDR
 186
 187 #define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM
 188 #define CONFIG_SYS_INIT_RAM_ADDR       IRAM_BASE_ADDR
 189 #define CONFIG_SYS_INIT_RAM_SIZE       IRAM_SIZE
 190
 191 #define CONFIG_SYS_INIT_SP_OFFSET \
 192         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 193 #define CONFIG_SYS_INIT_SP_ADDR \
 194         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 195
 196 /* environment organization */
 197 #define CONFIG_ENV_SIZE         (8 * 1024)
 198 #define CONFIG_ENV_OFFSET               (768 * 1024)
 199 #define CONFIG_ENV_SECT_SIZE            (64 * 1024)
 200 #define CONFIG_ENV_SPI_BUS              CONFIG_SF_DEFAULT_BUS
 201 #define CONFIG_ENV_SPI_CS               CONFIG_SF_DEFAULT_CS
 202 #define CONFIG_ENV_SPI_MODE             CONFIG_SF_DEFAULT_MODE
 203 #define CONFIG_ENV_SPI_MAX_HZ           CONFIG_SF_DEFAULT_SPEED
 204
 205 #ifndef CONFIG_SYS_DCACHE_OFF
 206 #endif
 207
 208 #define CONFIG_SYS_FSL_USDHC_NUM        3
 209
 210 /* Framebuffer */
 211 #define CONFIG_VIDEO
 212 #ifdef CONFIG_VIDEO
 213 #define CONFIG_VIDEO_IPUV3
 214 #define CONFIG_CFB_CONSOLE
 215 #define CONFIG_VGA_AS_SINGLE_DEVICE
 216 #define CONFIG_SYS_CONSOLE_FG_COL 0xFF
 217 #define CONFIG_SYS_CONSOLE_BG_COL 0x00
 218 #define CONFIG_HIDE_LOGO_VERSION
 219 #define CONFIG_IMX_HDMI
 220 #define CONFIG_IMX_VIDEO_SKIP
 221 #define CONFIG_CMD_BMP
 222 #endif
 223
 224 #define CONFIG_PWM_IMX
 225 #define CONFIG_IMX6_PWM_PER_CLK 66000000
 226
 227 #define CONFIG_PCI
 228 #define CONFIG_PCI_PNP
 229 #define CONFIG_PCI_SCAN_SHOW
 230 #define CONFIG_PCIE_IMX
 231 #define CONFIG_PCIE_IMX_PERST_GPIO      IMX_GPIO_NR(7, 12)
 232 #define CONFIG_PCIE_IMX_POWER_GPIO      IMX_GPIO_NR(1, 5)
 233
 234 #define CONFIG_RTC_RX8010SJ
 235 #define CONFIG_SYS_RTC_BUS_NUM 2
 236 #define CONFIG_SYS_I2C_RTC_ADDR 0x32
 237
 238 /* I2C Configs */
 239 #define CONFIG_SYS_I2C
 240 #define CONFIG_SYS_I2C_MXC
 241 #define CONFIG_SYS_I2C_SPEED              100000
 242 #define CONFIG_SYS_I2C_MXC_I2C1
 243 #define CONFIG_SYS_I2C_MXC_I2C2
 244 #define CONFIG_SYS_I2C_MXC_I2C3
 245
 246 #define CONFIG_SYS_NUM_I2C_BUSES        11
 247 #define CONFIG_SYS_I2C_MAX_HOPS         1
 248 #define CONFIG_SYS_I2C_BUSES    {       {0, {I2C_NULL_HOP} }, \
 249                                         {1, {I2C_NULL_HOP} }, \
 250                                         {2, {I2C_NULL_HOP} }, \
 251                                         {0, {{I2C_MUX_PCA9547, 0x70, 0} } }, \
 252                                         {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
 253                                         {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \
 254                                         {0, {{I2C_MUX_PCA9547, 0x70, 3} } }, \
 255                                         {0, {{I2C_MUX_PCA9547, 0x70, 4} } }, \
 256                                         {0, {{I2C_MUX_PCA9547, 0x70, 5} } }, \
 257                                         {0, {{I2C_MUX_PCA9547, 0x70, 6} } }, \
 258                                         {0, {{I2C_MUX_PCA9547, 0x70, 7} } }, \
 259                                 }
 260
 261 #define CONFIG_BCH
 262
 263 #endif  /* __GE_BX50V3_CONFIG_H */