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1 /*
2  * Copyright (C) 2015 Timesys Corporation
3  * Copyright (C) 2015 General Electric Company
4  * Copyright (C) 2014 Advantech
5  * Copyright (C) 2012 Freescale Semiconductor, Inc.
6  *
7  * Configuration settings for the GE MX6Q Bx50v3 boards.
8  *
9  * SPDX-License-Identifier:     GPL-2.0+
10  */
11
12 #ifndef __GE_BX50V3_CONFIG_H
13 #define __GE_BX50V3_CONFIG_H
14
15 #include <asm/arch/imx-regs.h>
16 #include <asm/mach-imx/gpio.h>
17
18 #define BX50V3_BOOTARGS_EXTRA
19 #if defined(CONFIG_TARGET_GE_B450V3)
20 #define CONFIG_BOARD_NAME       "General Electric B450v3"
21 #elif defined(CONFIG_TARGET_GE_B650V3)
22 #define CONFIG_BOARD_NAME       "General Electric B650v3"
23 #elif defined(CONFIG_TARGET_GE_B850V3)
24 #define CONFIG_BOARD_NAME       "General Electric B850v3"
25 #undef BX50V3_BOOTARGS_EXTRA
26 #define BX50V3_BOOTARGS_EXTRA   "video=DP-1:1024x768@60 " \
27                                 "video=HDMI-A-1:1024x768@60 "
28 #else
29 #define CONFIG_BOARD_NAME       "General Electric BA16 Generic"
30 #endif
31
32 #define CONFIG_MXC_UART_BASE    UART3_BASE
33 #define CONSOLE_DEV     "ttymxc2"
34
35 #define CONFIG_SUPPORT_EMMC_BOOT
36
37
38 #include "mx6_common.h"
39 #include <linux/sizes.h>
40
41 #define CONFIG_CMDLINE_TAG
42 #define CONFIG_SETUP_MEMORY_TAGS
43 #define CONFIG_INITRD_TAG
44 #define CONFIG_REVISION_TAG
45 #define CONFIG_SYS_MALLOC_LEN           (10 * SZ_1M)
46
47 #define CONFIG_HW_WATCHDOG
48 #define CONFIG_IMX_WATCHDOG
49 #define CONFIG_WATCHDOG_TIMEOUT_MSECS 6000
50
51 #define CONFIG_LAST_STAGE_INIT
52
53 #define CONFIG_MXC_UART
54
55 #define CONFIG_MXC_OCOTP
56
57 /* SATA Configs */
58 #ifdef CONFIG_CMD_SATA
59 #define CONFIG_SYS_SATA_MAX_DEVICE      1
60 #define CONFIG_DWC_AHSATA_PORT_ID       0
61 #define CONFIG_DWC_AHSATA_BASE_ADDR     SATA_ARB_BASE_ADDR
62 #define CONFIG_LBA48
63 #endif
64
65 /* MMC Configs */
66 #define CONFIG_FSL_ESDHC
67 #define CONFIG_FSL_USDHC
68 #define CONFIG_SYS_FSL_ESDHC_ADDR      0
69 #define CONFIG_BOUNCE_BUFFER
70
71 /* USB Configs */
72 #ifdef CONFIG_USB
73 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
74 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
75 #define CONFIG_MXC_USB_PORTSC   (PORT_PTS_UTMI | PORT_PTS_PTW)
76 #define CONFIG_MXC_USB_FLAGS    0
77
78 #define CONFIG_USBD_HS
79 #define CONFIG_USB_GADGET_MASS_STORAGE
80 #endif
81
82 /* Networking Configs */
83 #ifdef CONFIG_NET
84 #define CONFIG_FEC_MXC
85 #define CONFIG_MII
86 #define IMX_FEC_BASE                    ENET_BASE_ADDR
87 #define CONFIG_FEC_XCV_TYPE             RGMII
88 #define CONFIG_ETHPRIME         "FEC"
89 #define CONFIG_FEC_MXC_PHYADDR          4
90 #define CONFIG_PHY_ATHEROS
91 #endif
92
93 /* Serial Flash */
94 #ifdef CONFIG_CMD_SF
95 #define CONFIG_SF_DEFAULT_BUS           0
96 #define CONFIG_SF_DEFAULT_CS            0
97 #define CONFIG_SF_DEFAULT_SPEED 20000000
98 #define CONFIG_SF_DEFAULT_MODE          SPI_MODE_0
99 #endif
100
101 /* allow to overwrite serial and ethaddr */
102 #define CONFIG_ENV_OVERWRITE
103
104 #define CONFIG_LOADADDR 0x12000000
105
106 #define CONFIG_EXTRA_ENV_SETTINGS \
107         "bootcause=POR\0" \
108         "bootlimit=10\0" \
109         "image=/boot/fitImage\0" \
110         "fdt_high=0xffffffff\0" \
111         "dev=mmc\0" \
112         "devnum=1\0" \
113         "rootdev=mmcblk0p\0" \
114         "quiet=quiet loglevel=0\0" \
115         "console=" CONSOLE_DEV "\0" \
116         "setargs=setenv bootargs root=/dev/${rootdev}${partnum} " \
117                 "ro rootwait cma=128M " \
118                 "bootcause=${bootcause} " \
119                 "${quiet} console=${console} ${rtc_status} " \
120                 BX50V3_BOOTARGS_EXTRA "\0" \
121         "doquiet=" \
122                 "if ext2load ${dev} ${devnum}:5 0x7000A000 /boot/console; " \
123                         "then setenv quiet; fi\0" \
124         "hasfirstboot=" \
125                 "ext2load ${dev} ${devnum}:${partnum} 0x7000A000 " \
126                 "/boot/bootcause/firstboot\0" \
127         "swappartitions=" \
128                 "setexpr partnum 3 - ${partnum}\0" \
129         "failbootcmd=" \
130                 "msg=\"Monitor failed to start.  Try again, or contact GE Service for support.\"; " \
131                 "echo $msg; " \
132                 "setenv stdout vga; " \
133                 "echo \"\n\n\n\n    \" $msg; " \
134                 "setenv stdout serial; " \
135                 "mw.b 0x7000A000 0xbc; " \
136                 "mw.b 0x7000A001 0x00; " \
137                 "ext4write ${dev} ${devnum}:5 0x7000A000 /boot/failures 2\0" \
138         "altbootcmd=" \
139                 "run doquiet; " \
140                 "setenv partnum 1; run hasfirstboot || setenv partnum 2; " \
141                 "run hasfirstboot || setenv partnum 0; " \
142                 "if test ${partnum} != 0; then " \
143                         "setenv bootcause REVERT; " \
144                         "run swappartitions loadimage doboot; " \
145                 "fi; " \
146                 "run failbootcmd\0" \
147         "loadimage=" \
148                 "ext2load ${dev} ${devnum}:${partnum} ${loadaddr} ${image}\0" \
149         "doboot=" \
150                 "echo Booting from ${dev}:${devnum}:${partnum} ...; " \
151                 "run setargs; " \
152                 "bootm ${loadaddr}#conf@${confidx}\0" \
153         "tryboot=" \
154                 "setenv partnum 1; run hasfirstboot || setenv partnum 2; " \
155                 "run loadimage || run swappartitions && run loadimage || " \
156                 "setenv partnum 0 && echo MISSING IMAGE;" \
157                 "run doboot; " \
158                 "run failbootcmd\0" \
159
160 #define CONFIG_MMCBOOTCOMMAND \
161         "if mmc dev ${devnum}; then " \
162                 "run doquiet; " \
163                 "run tryboot; " \
164         "fi; " \
165
166 #define CONFIG_USBBOOTCOMMAND \
167         "echo Unsupported; " \
168
169 #ifdef CONFIG_CMD_USB
170 #define CONFIG_BOOTCOMMAND CONFIG_USBBOOTCOMMAND
171 #else
172 #define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND
173 #endif
174
175 #define CONFIG_ARP_TIMEOUT     200UL
176
177 /* Miscellaneous configurable options */
178
179 #define CONFIG_SYS_MEMTEST_START       0x10000000
180 #define CONFIG_SYS_MEMTEST_END         0x10010000
181 #define CONFIG_SYS_MEMTEST_SCRATCH     0x10800000
182
183 #define CONFIG_SYS_LOAD_ADDR           CONFIG_LOADADDR
184
185 /* Physical Memory Map */
186 #define CONFIG_NR_DRAM_BANKS           1
187 #define PHYS_SDRAM                     MMDC0_ARB_BASE_ADDR
188
189 #define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM
190 #define CONFIG_SYS_INIT_RAM_ADDR       IRAM_BASE_ADDR
191 #define CONFIG_SYS_INIT_RAM_SIZE       IRAM_SIZE
192
193 #define CONFIG_SYS_INIT_SP_OFFSET \
194         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
195 #define CONFIG_SYS_INIT_SP_ADDR \
196         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
197
198 /* environment organization */
199 #define CONFIG_ENV_SIZE         (8 * 1024)
200 #define CONFIG_ENV_OFFSET               (768 * 1024)
201 #define CONFIG_ENV_SECT_SIZE            (64 * 1024)
202 #define CONFIG_ENV_SPI_BUS              CONFIG_SF_DEFAULT_BUS
203 #define CONFIG_ENV_SPI_CS               CONFIG_SF_DEFAULT_CS
204 #define CONFIG_ENV_SPI_MODE             CONFIG_SF_DEFAULT_MODE
205 #define CONFIG_ENV_SPI_MAX_HZ           CONFIG_SF_DEFAULT_SPEED
206
207 #ifndef CONFIG_SYS_DCACHE_OFF
208 #endif
209
210 #define CONFIG_SYS_FSL_USDHC_NUM        3
211
212 /* Framebuffer */
213 #define CONFIG_VIDEO
214 #ifdef CONFIG_VIDEO
215 #define CONFIG_VIDEO_IPUV3
216 #define CONFIG_CFB_CONSOLE
217 #define CONFIG_VGA_AS_SINGLE_DEVICE
218 #define CONFIG_SYS_CONSOLE_FG_COL 0xFF
219 #define CONFIG_SYS_CONSOLE_BG_COL 0x00
220 #define CONFIG_HIDE_LOGO_VERSION
221 #define CONFIG_IMX_HDMI
222 #define CONFIG_IMX_VIDEO_SKIP
223 #define CONFIG_CMD_BMP
224 #endif
225
226 #define CONFIG_PWM_IMX
227 #define CONFIG_IMX6_PWM_PER_CLK 66000000
228
229 #define CONFIG_PCI
230 #define CONFIG_PCI_PNP
231 #define CONFIG_PCI_SCAN_SHOW
232 #define CONFIG_PCIE_IMX
233 #define CONFIG_PCIE_IMX_PERST_GPIO      IMX_GPIO_NR(7, 12)
234 #define CONFIG_PCIE_IMX_POWER_GPIO      IMX_GPIO_NR(1, 5)
235
236 #define CONFIG_RTC_RX8010SJ
237 #define CONFIG_SYS_RTC_BUS_NUM 2
238 #define CONFIG_SYS_I2C_RTC_ADDR 0x32
239
240 /* I2C Configs */
241 #define CONFIG_SYS_I2C
242 #define CONFIG_SYS_I2C_MXC
243 #define CONFIG_SYS_I2C_SPEED              100000
244 #define CONFIG_SYS_I2C_MXC_I2C1
245 #define CONFIG_SYS_I2C_MXC_I2C2
246 #define CONFIG_SYS_I2C_MXC_I2C3
247
248 #define CONFIG_SYS_NUM_I2C_BUSES        11
249 #define CONFIG_SYS_I2C_MAX_HOPS         1
250 #define CONFIG_SYS_I2C_BUSES    {       {0, {I2C_NULL_HOP} }, \
251                                         {1, {I2C_NULL_HOP} }, \
252                                         {2, {I2C_NULL_HOP} }, \
253                                         {0, {{I2C_MUX_PCA9547, 0x70, 0} } }, \
254                                         {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
255                                         {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \
256                                         {0, {{I2C_MUX_PCA9547, 0x70, 3} } }, \
257                                         {0, {{I2C_MUX_PCA9547, 0x70, 4} } }, \
258                                         {0, {{I2C_MUX_PCA9547, 0x70, 5} } }, \
259                                         {0, {{I2C_MUX_PCA9547, 0x70, 6} } }, \
260                                         {0, {{I2C_MUX_PCA9547, 0x70, 7} } }, \
261                                 }
262
263 #define CONFIG_BCH
264
265 #endif  /* __GE_BX50V3_CONFIG_H */